Output Stage; Table 31. Counting Direction And Encoding Signals; Figure 58. Both Ti0 And Ti1 Quadrature Decoder Counting; Figure 59. Output Stage Block Diagram - Holtek HT32F54231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253

Table 31. Counting Direction and Encoding Signals

Counting Mode
Counting on TI0 only
(SMSEL = 0x1)
Counting on TI1 only
(SMSEL = 0x2)
Counting on TI0 and TI1
(SMSEL = 0x3)
TI0
TI1
Up
Down

Figure 58. Both TI0 and TI1 Quadrature Decoder Counting

Output Stage

The GPTM has four channels for compare match, single pulse or PWM output function. The
channel output GT_CHxO is controlled by the CHxOM, CHxP and CHxE bits in the corresponding
CHxOCFR, CHPOLR and CHCTR registers.
CNTR
CHxCCR
f
CLKIN

Figure 59. Output Stage Block Diagram

Rev. 1.00
Level
Rising
TI1S1 = High Down
TI1S1 = Low
TI0S0 = High
TI0S0 = Low
TI1S1 = High Down
TI1S1 = Low
TI0S0 = High
TI0S0 = Low
Note: "—" → means "no counting"; "X" → impossible
CHxOREF
Output Mode
Controller
CHxP
CHxOM
x: 0 ~ 3
237 of 576
TI0S0
Falling Rising
Up
Up Down
— —
— — Down
Up
Up Down
X X
X X Down
Quadrature Decoder
Counting on Both TI0 & TI1
(CH0P = 0, CH1P = 0)
Output Enable
Controller
CHxE
TI1S1
Falling
— —
— —
Up Down
Up
X X
X X
Up Down
Up
GT_CHxO
CHxOREF
CHxCMP Event
January 28, 2022