32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Register Map
The following table shows the Watchdog Timer registers and reset values.
Table 46. Watchdog Timer Register Map
Register
WDTCR
0x000
WDTMR0
0x004
WDTMR1
0x008
WDTSR
0x00C
WDTPR
0x010
WDTCSR
0x018
Register Descriptions
Watchdog Timer Control Register – WDTCR
This register is used to reload the Watchdog timer.
Offset:
0x000
Reset value: 0x0000_0000
31
Type/Reset
WO
0 WO
23
Type/Reset
WO
0 WO
15
Type/Reset
7
Type/Reset
Bits
Field
[31:16]
RSKEY
[0]
WDTRS
Rev. 1.00
Offset
Watchdog Timer Control Register
Watchdog Timer Mode Register 0
Watchdog Timer Mode Register 1
Watchdog Timer Status Register
Watchdog Timer Protection Register
Watchdog Timer Clock Selection Register
30
29
28
0 WO
0 WO
22
21
20
0 WO
0 WO
14
13
12
6
5
4
Reserved
Descriptions
Watchdog Timer Reload Lock Key
The RSKEY [15:0] bits should be written with a 0x5FA0 value to enable the WDT
reload operation function. Writing any other value except 0x5FA0 in this field will
abort the write operation.
Watchdog Timer Reload
0: No effect
1: Reload Watchdog Timer
This bit is used to reload the Watchdog timer counter as a WDTV value which
is stored in the WDTMR0 register. It is set to 1 by software and cleared to 0 by
hardware automatically.
413 of 576
Description
27
26
RSKEY
0 WO
0 WO
0 WO
19
18
RSKEY
0 WO
0 WO
0 WO
11
10
Reserved
3
2
Reset Value
0x0000_0000
0x0000_0FFF
0x0000_7FFF
0x0000_0000
0x0000_0000
0x0000_0000
25
24
0 WO
0
17
16
0 WO
0
9
8
1
0
WDTRS
WO
0
January 28, 2022
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