Register Descriptions; Global Clock Configuration Register - Gcfgr - Holtek HT32F54231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253

Register Descriptions

Global Clock Configuration Register – GCFGR
This register specifies the clock source for PLL/CKOUT.
Offset: 0x000
Reset value: 0x0000_0302
31
Type/Reset WC 0 WC
23
Type/Reset
15
Type/Reset RW 0 RW
7
Type/Reset
Bits Field
[31:29] LPMOD
[15:11] CKREFPRE
[8] PLLSRC
[2:0] CKOUTSRC
Rev. 1.00
30 29 28
LPMOD
0 RO 0
22 21 20
14 13 12
CKREFPRE
0 RW 0 RW
6 5 4
Reserved
Descriptions
Lower Power Mode Status
000: When chip is in running mode
001: When chip once entered Sleep mode
010: When chip once entered Deep-Sleep1 mode
011: When chip once entered Deep-Sleep2 mode
Others: Reserved
Set by hardware. Reset by software writing b11x.
CK_REF Clock Prescaler Selection
CK_REF = CK_PLL / (CKREFPRE + 1) / 2
00000: CK_REF = CK_PLL / 2
00001: CK_REF = CK_PLL / 4
...
11111: CK_REF = CK_PLL / 64
Set and reset by software to control the CK_REF clock prescaler setting.
PLL Clock Source Selection
0: External 4 ~ 16 MHz crystal oscillator clock is selected (HSE)
1: Internal 8 MHz RC oscillator clock is selected (HSI)
Set and reset by software to control the PLL clock source.
CKOUT Clock Source Selection
000: CK_REF is selected, CK_REF = CK_PLL / (CKREFPRE + 1) / 2
001: (HCLKC / 16) is selected
010: (CK_SYS / 16) is selected
011: (CK_HSE / 16) is selected
100: (CK_HSI / 16) is selected
101: CK_LSE is selected
110: CK_LSI is selected
111: Reserved
Set and reset by software to control the CKOUT clock source.
90 of 576
27 26
Reserved
19 18
Reserved
11 10
0 RW 0
3 2
CKOUTSRC
RW 0 RW
25 24
17 16
9 8
Reserved PLLSRC
RW 1
1 0
1 RW 0
January 28, 2022