32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
SPI Clock Prescaler Register – SPICPR
This register specifies the SPI clock prescaler ratio.
Offset:
0x00C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
RW
0 RW
7
Type/Reset
RW
0 RW
Bits
Field
[15:0]
CP
Rev. 1.00
30
29
28
22
21
20
14
13
12
0 RW
0 RW
6
5
4
0 RW
0 RW
Descriptions
SPI Clock Prescaler
The SPI clock (SCK) is determined by the following equation:
f
= f
/ (2 × (CP + 1)), where the CP ranges is from 0 to 65535
SCK
PCLK
Note: For the SPI master mode, the APB clock (f
than the SPI SCK output.
462 of 576
27
26
Reserved
19
18
Reserved
11
10
CP
0 RW
0 RW
0 RW
3
2
CP
0 RW
0 RW
0 RW
) must be at least 2 times faster
PCLK
25
24
17
16
9
8
0 RW
0
1
0
0 RW
0
January 28, 2022
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