Holtek HT32F54231 User Manual page 4

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
AHB Configuration Register - AHBCFGR ...................................................................................... 96
AHB Clock Control Register - AHBCCR ........................................................................................ 97
APB Configuration Register - APBCFGR ....................................................................................... 99
APB Clock Control Register 0 - APBCCR0 .................................................................................. 100
APB Clock Control Register 1 - APBCCR1 .................................................................................. 102
Clock Source Status Register - CKST ......................................................................................... 104
APB Peripheral Clock Selection Register 0 - APBPCSR0 ........................................................... 105
APB Peripheral Clock Selection Register 1 - APBPCSR1 ........................................................... 107
HSI Control Register - HSICR ...................................................................................................... 109
HSI Auto Trimming Counter Register - HSIATCR .........................................................................110
APB Peripheral Clock Selection Register 2 - APBPCSR2 ............................................................111
MCU Debug Control Register - MCUDBGCR ...............................................................................112
7 Reset Control Unit (RSTCU) .............................................................................. 115
Introduction ........................................................................................................................ 115
Functional Descriptions ..................................................................................................... 115
Power-On Reset ............................................................................................................................115
System Reset ................................................................................................................................116
AHB and APB Unit Reset ...............................................................................................................116
Register Map ..................................................................................................................... 116
Register Descriptions ......................................................................................................... 117
Global Reset Status Register - GRSR ..........................................................................................117
AHB Peripheral Reset Register - AHBPRSTR ..............................................................................118
APB Peripheral Reset Register 0 - APBPRSTR0 .........................................................................119
APB Peripheral Reset Register 1 - APBPRSTR1 ........................................................................ 121
8 General Purpose I/O (GPIO) ............................................................................... 123
Introduction ........................................................................................................................ 123
Features ............................................................................................................................. 124
Functional Descriptions ..................................................................................................... 124
Default GPIO Pin Configuration .................................................................................................... 124
General Purpose I/O - GPIO ........................................................................................................ 124
GPIO Locking Mechanism ............................................................................................................ 126
Register Map ..................................................................................................................... 126
Register Descriptions ......................................................................................................... 128
Port A Data Direction Control Register - PADIRCR ..................................................................... 128
Port A Input Function Enable Control Register - PAINER ............................................................ 129
Port A Pull-Up Selection Register - PAPUR ................................................................................. 130
Port A Pull-Down Selection Register - PAPDR ............................................................................ 131
Port A Open-Drain Selection Register - PAODR .......................................................................... 132
Port A Drive Current Selection Register - PADRVR ..................................................................... 133
Port A Lock Register - PALOCKR ................................................................................................ 134
Port A Data Input Register - PADINR ........................................................................................... 135
Port A Output Data Register - PADOUTR .................................................................................... 135
Rev. 1.00 4 of 576 January 28, 2022