Table Of Contents - Holtek HT32F54231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253

Table of Contents

1 Introduction ........................................................................................................... 25
Overview .............................................................................................................................. 25
Features ............................................................................................................................... 25
Device Information ............................................................................................................... 30
Block Diagram ..................................................................................................................... 31
2 Document Conventions ....................................................................................... 33
3 System Architecture ............................................................................................. 34
Arm ® Cortex ® -M0+ Processor .............................................................................................. 34
Bus Architecture ................................................................................................................... 35
Memory Organization .......................................................................................................... 36
Memory Map ................................................................................................................................... 37
Embedded Flash Memory ............................................................................................................... 42
Embedded SRAM Memory ............................................................................................................. 42
AHB Peripherals ............................................................................................................................. 42
APB Peripherals ............................................................................................................................. 42
4 Flash Memory Controller (FMC) .......................................................................... 43
Introduction .......................................................................................................................... 43
Features ............................................................................................................................... 43
Functional Descriptions ....................................................................................................... 44
Flash Memory Map ......................................................................................................................... 44
Flash Memory Architecture ............................................................................................................. 45
Wait State Setting ........................................................................................................................... 45
Booting Configuration ..................................................................................................................... 46
Page Erase ..................................................................................................................................... 46
Mass Erase ..................................................................................................................................... 48
Word Programming ......................................................................................................................... 49
Option Byte Description .................................................................................................................. 50
Page Erase/Program Protection ..................................................................................................... 51
Security Protection .......................................................................................................................... 52
Register Map ....................................................................................................................... 53
Register Descriptions ........................................................................................................... 54
Flash Target Address Register - TADR .......................................................................................... 54
Flash Write Data Register - WRDR ............................................................................................... 55
Flash Operation Command Register - OCMR ............................................................................... 56
Flash Operation Control Register - OPCR ..................................................................................... 57
Flash Operation Interrupt Enable Register - OIER ........................................................................ 58
Flash Operation Interrupt and Status Register - OISR .................................................................. 59
Flash Page Erase/Program Protection Status Register - PPSR .................................................... 61
Flash Security Protection Status Register - CPSR ........................................................................ 62
Rev. 1.00 2 of 576 January 28, 2022