Single Pulse Mode; Figure 66. Single Pulse Mode - Holtek HT32F54231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253

Single Pulse Mode

Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable
bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be
sourced from the STI signal rising edge or by setting the TME bit to 1 using software. Setting the
TME bit to 1 or a trigger from the STI signal rising edge can generate a pulse and then keep the
TME bit at a high state until the update event occurs or the TME bit is written to 0 by software.
If the TME bit is cleared to 0 using software, the counter will be stopped and its value held. If the
TME bit is automatically cleared to 0 by a hardware update event, the counter will be reinitialized.
Counter Value
CRR
CHxCCR
TME bit
Trigger by STI
STI
CHxOREF
Delay
(PWM1)
Delay
(PWM2)
CHxOREF
Min. delay
(PWM1)
(PWM2)
Min. delay
UEVIF
CHxCCIF

Figure 66. Single Pulse Mode

Rev. 1.00
Counter
reinitialized
Cleared by
Trigger by S/W
Update Event
Delay
Delay
Delay
Delay
Flag is set by update event
and cleard by S/W
Flag is set by compare match and
cleared by S/W
242 of 576
Counter stopped
and held
Time
Cleared by S/W
CHxIMAE=0
CHxIMAE=1
January 28, 2022