Led Com Enable Register - Ledcer - Holtek HT32F54231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Bits Field
[0] LEDEN
LED COM Enable Register – LEDCER
This register is used to control the COMy enable, (y = 0 ~ 11).
Offset: 0x004
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
COM7EN COM6EN
Type/Reset RW 0 RW
Bits Field
[11:0] COMyEN
Rev. 1.00
Descriptions
LEDC Enable Bit
0: Disable
1: Enable
The LEDC state machine will be enabled when this bit is set to 1. If this bit is set
to 0, the state machine will continue to output until the current frame operation is
completed, then the state of the state machine will be cleared and finally the LEDEN
bit will be cleared to zero by the hardware.
Therefore, the LEDEN bit must be polled continuously after clearing the LEDEN bit
has been executed, the LED controller will not actually cease operation until the
LEDEN becomes 0.
When the LEDEN bit is set high, the LEDSRC, LEDPS and DTYNUM bit field
contents should remain unchanged. Even if new data is written into these bit fields,
they are invalid, however the LEDDR and DEADNUM bit fields can be modified. It is
recommended to update in the frame interrupt subroutine.
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
COM5EN COM4EN
0 RW 0 RW
Descriptions
COMy Enable Bit (y = 0 ~ 11)
0: COMy disable
1: COMy enable
In a complete frame period, tframe, the enabled COMs will be scanned from low
number to high number.
Assuming that four 8-segment LEDs are used, the COM7EN, COM6EN, COM5EN
and COM0EN bits are set to 1 and the remaining bits are set to zero. Here COM0,
COM5, COM6 and COM7 will be scanned successively within a complete frame
period. The scanning time of for each COM port is equal to 1/4 t
subdivided into dead time duty and COM duty. Users can adjust the dead time duty
to change the LED brightness.
Therefore, a complete frame scans COM0 → COM5 → COM6 → COM7 in sequence.
If no COMyEN bit is set, the LEDC will not operate after LEDEN is enabled.
541 of 576
27 26
Reserved
19 18
Reserved
11 10
COM11EN COM10EN COM9EN
RW 0 RW 0 RW
3 2
COM3EN COM2EN
0 RW 0 RW 0 RW
25 24
17 16
9 8
COM8EN
0 RW 0
1 0
COM1EN COM0EN
0 RW 0
, which is
frame
January 28, 2022