Power Control Register - Pwrcr - Holtek HT32F54231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Power Control Register – PWRCR
This register provides power control bits for the different kinds of power saving modes.
Offset: 0x104
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
ULDOSTS
Type/Reset RO 0
7
ULDOON
Type/Reset RW 0
Bits Field
[19:18] WUP1TYPE WAKEUP1 Signal Trigger Type
[17:16] WUP0TYPE WAKEUP0 Signal Trigger Type
[15] ULDOSTS
[10] WUP1EN
Rev. 1.00
30 29 28
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved
Descriptions
WUP1TYPE WAKEUP1 Signal Trigger Type
[1:0]
0 0 Positive-edge Triggered
0
1 Negative-edge Triggered
1 0 High-level Sensitive
1 1 Low-level Sensitive
WUP0TYPE WAKEUP0 Signal Trigger Type
[1:0]
0 0 Positive-edge Triggered
0 1 Negative-edge Triggered
1
0 High-level Sensitive
1 1 Low-level Sensitive
Ultra-low Power Regulator Status
This bit is set to 1 if the ULDOON bit in this register has been cleared to 1 after MCU
is wakeup from the Deep-Sleep2 mode. This bit is cleared to 0 if the ULDOON bit
has been set to 0 or if a POR/PDR reset occurred.
External WAKEUP1 Pin Enable
0: Disable WAKEUP1 pin function
1: Enable WAKEUP1 pin function
The software can set the WUP1EN bit as 1 to enable the WAKEUP1 pin function
before entering the power saving mode. When WUP1EN = 1, a change on the
WAKEUP1 pin wakes up the system from the power saving mode. If the WAKEUP1
pin is active high, this bit will set an input pull down mode.
76 of 576
27 26
Reserved
19 18
WUP1TYPE
RW 0 RW 0 RW
11 10
WUP1EN Reserved
RW 0
3 2
LDOOFF LDOLCM Reserved
RW 0 RW 0
25 24
17 16
WUP0TYPE
0 RW 0
9 8
WUP0EN
RW 0
1 0
PWCURST
WO 0
January 28, 2022