32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Bits
Field
[18:16]
MMSEL
Rev. 1.00
Descriptions
Master Mode Selection
Master mode selection is used to select the MTO signal source which is used to
synchronize the other slave timer.
MMSEL [2:0]
Mode
000
Reset Mode
001
Enable Mode
010
Update Mode
Capture/Compare
011
Mode
100
Compare Mode 0
101
Compare Mode 1
110
Compare Mode 2
111
Compare Mode 3
251 of 576
Descriptions
The MTO signal in the Reset mode is an output
derived from one of the following cases:
1. Software setting UEVG bit
2. The STI trigger input signal which will be output
on the MTO signal line when the Timer is used
in the slave Restart mode
The Counter Enable signal is used as the trigger
output.
The update event is used as the trigger output
according to one of the following cases when the
UEVDIS bit is cleared to 0:
1. Counter overflow / underflow
2. Software setting UEVG
3. Slave trigger input when used in slave restart
mode
When a Channel 0 capture or compare match
event occurs, it will generate a positive pulse
used as the master trigger output.
The Channel 0 Output reference signal named
CH0OREF is used as the trigger output.
The Channel 1 Output reference signal named
CH1OREF is used as the trigger output.
The Channel 2 Output reference signal named
CH2OREF is used as the trigger output.
The Channel 3 Output reference signal named
CH3OREF is used as the trigger output.
January 28, 2022
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