Clock Controller; Figure 78. Mctm Clock Source Selection - Holtek HT32F54231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253

Clock Controller

The following describes the Timer Module clock controller which determines the internal prescaler
counter clock source.
Internal APB clock f
▆
The default internal clock source is the APB clock f
prescaler when the slave mode is disabled. When the slave mode selection bits SMSEL are set to
0x4, 0x5 or 0x6, the internal APB clock f
STIED
▆
The counter prescaler can count during each rising edge of the STI signal. This mode can be
selected by setting the SMSEL field to 0x7 in the MDCFR register. Here the counter will act
as an event counter. The input event, known as STI here, can be selected by setting the TRSEL
field to an available value except the value of 0x0. When the STI signal is selected as the clock
source, the internal edge detection circuitry will generate a clock pulse during each STI signal
rising edge to drive the counter prescaler. It is important to note that if the TRSEL field is set to
0x0 to select the software UEV1G bit as the trigger source, then when the SMSEL field is set to
0x7, the counter will be updated instead of counting.
f
CLKIN
(Internal APB clock)
CK_PSC
CLK
STIED
(Trigger events)
TRSEL
SMSEL
Start/Stop

Figure 78. MCTM Clock Source Selection

Rev. 1.00
CLKIN
PSCR CRR
CK_CNT
CLK
PSC Prescaler CNTR
Reset
Reset
Overflow /
UEV1G bit
Underflow
291 of 576
which is used to drive the counter
CLKIN
is the counter prescaler driving clock source.
CLKIN
REPR
Repetition
Down Counter
Dec
TM_CNT
Slave Restart
mode trigger
Update Event 1
January 28, 2022