32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
DUALEN
SEL (SELAP=0)
SEL (SELAP=1)
SCK
½
SCK
MOSI
RX[6]
MISO
RX[7]
Data sampled
Figure 165. SPI Dual Mode Bit Sequence – CPOL = 1, CPHA = 0, DFL = 0x8 (16-bit), MSB
Transmitted First
DUALEN
SEL (SELAP=0)
SEL (SELAP=1)
SCK
½
SCK
MOSI
MISO
Figure 166. SPI Dual Mode Bit Sequence – CPOL = 1, CPHA = 1, DFL = 0x8 (16-bit), MSB
Transmitted First
Rev. 1.00
RX[4]
RX[2]
RX[0]
RX[5]
RX[3]
RX[1]
RX[6]
RX[4]
RX[2]
RX[7]
RX[5]
RX[3]
Data sampled
452 of 576
RX[14]
RX[12]
RX[10]
RX[15]
RX[13]
RX[11]
RX[0]
RX[14]
RX[12]
RX[10]
RX[1]
RX[15]
RX[13]
RX[11]
RX[8]
RX[9]
RX[8]
RX[9]
January 28, 2022
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