Holtek HT32F54231 User Manual page 14

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
UART Test Register - URTSTR .................................................................................................... 505
24 Peripheral Direct Memory Access (PDMA) ..................................................... 506
Introduction ........................................................................................................................ 506
Features ............................................................................................................................. 506
Functional Description ....................................................................................................... 507
AHB Master .................................................................................................................................. 507
PDMA Channel ............................................................................................................................. 507
PDMA Request Mapping .............................................................................................................. 507
Channel Transfer .......................................................................................................................... 508
Channel Priority ............................................................................................................................ 508
Transfer Request .......................................................................................................................... 509
Address Mode ............................................................................................................................... 509
Auto-Reload .................................................................................................................................. 510
Transfer Interrupt .......................................................................................................................... 510
Register Map ..................................................................................................................... 511
Register Descriptions ......................................................................................................... 512
PDMA Channel n Control Register - PDMACHnCR (n = 0 ~ 5) ................................................... 512
PDMA Channel n Source Address Register - PDMACHnSADR (n = 0 ~ 5) ................................ 514
PDMA Channel n Destination Address Register - PDMACHnDADR (n = 0 ~ 5) ......................... 515
PDMA Channel n Transfer Size Register - PDMACHnTSR (n = 0 ~ 5) ....................................... 516
PDMA Channel n Current Transfer Size Register - PDMACHnCTSR (n = 0 ~ 5) ........................ 517
PDMA Interrupt Status Register - PDMAISR ............................................................................... 518
PDMA Interrupt Status Clear Register - PDMAISCR ................................................................... 519
PDMA Interrupt Enable Register - PDMAIER .............................................................................. 520
25 Divider (DIV) ...................................................................................................... 522
Introduction ........................................................................................................................ 522
Features ............................................................................................................................. 522
Functional Descriptions ..................................................................................................... 522
Register Map ..................................................................................................................... 523
Register Descriptions ......................................................................................................... 523
Divider Control Register - CR ...................................................................................................... 523
Dividend Data Register - DDR ..................................................................................................... 524
Divisor Data Register - DSR ........................................................................................................ 524
Quotient Data Register - QTR ...................................................................................................... 525
Remainder Data Register - RMR ................................................................................................. 525
26 Cyclic Redundancy Check (CRC) .................................................................... 526
Introduction ........................................................................................................................ 526
Features ............................................................................................................................. 526
Functional Descriptions ..................................................................................................... 527
CRC Computation ......................................................................................................................... 527
Byte and Bit Reversal for CRC Computation ................................................................................ 527
Rev. 1.00 14 of 576 January 28, 2022