Spi Interrupt Enable Register - Spiier - Holtek HT32F54231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
SPI Interrupt Enable Register – SPIIER
This register contains the corresponding SPI interrupt enable control bit.
Offset: 0x008
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
TOIEN
Type/Reset RW 0 RW
Bits Field
[7] TOIEN
[6] SAIEN
[5] MFIEN
[4] ROIEN
[3] WCIEN
[2] RXBNEIEN
[1] TXEIEN
[0] TXBEIEN
Rev. 1.00
30 29 28
22 21 20
14 13 12
6 5 4
SAIEN MFIEN ROIEN
0 RW 0 RW
Descriptions
Time Out Interrupt Enable
0: Disable
1: Enable
Slave Abort Interrupt Enable
0: Disable
1: Enable
Mode Fault Interrupt Enable
0: Disable
1: Enable
Read Overrun Interrupt Enable
0: Disable
1: Enable
Write Collision Interrupt Enable
0: Disable
1: Enable
RX Buffer Not Empty Interrupt Enable
0: Disable
1: Enable
An interrupt is generated when the RXBNE flag is set and RXBNEIEN is set. In the FIFO
mode, the interrupt being generated depends upon the RX FIFO trigger level setting.
Transmission Register Empty Interrupt Enable
0: Disable
1: Enable
The transmission register empty interrupt request will be generated when the TXE
flag and the TXEIEN bit are set.
TX Buffer Empty Interrupt Enable
0: Disable
1: Enable
The TX buffer empty interrupt request will be generated when the TXBE flag and
the TXBEIEN bit are set. In the FIFO mode, the interrupt request being generated
depends upon the TX FIFO trigger level setting.
461 of 576
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
WCIEN RXBNEIEN
0 RW 0 RW 0 RW
25 24
17 16
9 8
1 0
TXEIEN TXBEIEN
0 RW 0
January 28, 2022