Uart Divider Latch Register - Urdlr - Holtek HT32F54231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Bits Field
[1] OEI
UART Divider Latch Register – URDLR
The register is used to determine the UART clock divided ratio to generate the appropriate baud rate.
Offset: 0x024
Reset value: 0x0000_0010
31
Type/Reset
23
Type/Reset
15
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[15:0] BRD
Rev. 1.00
Descriptions
Overrun Error Indicator
An overrun error will occur only after the receive data register is full and when
the next character has been completely received in the receive shift register. The
character in the receive shift register will be overwritten when a new character is
received in the receive shift register after an overrun event occurs, but the data in
the receive shift register will not be transferred to the receive data register. The OEI
bit is used to indicate event as soon as it happens. Writing 1 to this bit clears the
flag.
30 29 28
22 21 20
14 13 12
0 RW 0 RW
6 5 4
0 RW 0 RW
Descriptions
Baud Rate Divider
The 16 bits define the UART clock divider ratio.
Baud Rate = CK_UART / BRD
Where the CK_UART clock is the clock connected to the UART module.
BRD = 16 ~ 65535 for the UART mode
504 of 576
27 26
Reserved
19 18
Reserved
11 10
BRD
0 RW 0 RW 0 RW
3 2
BRD
1 RW 0 RW 0 RW
25 24
17 16
9 8
0 RW 0
1 0
0 RW 0
January 28, 2022