32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Register Map
The following table shows the RTC registers and reset values. Note all the registers in this unit are
located at the V
Table 45. RTC Register Map
Register
RTCCNT
0x000
RTCCMP
0x004
RTCCR
0x008
RTCSR
0x00C
RTCIWEN
0x010
Register Descriptions
RTC Counter Register – RTCCNT
This register defines a 24-bit up-counter which is increased by the CK_SECOND clock.
Address:
0x000
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
RO
0 RO
15
Type/Reset
RO
0 RO
7
Type/Reset
RO
0 RO
Bits
Field
[23:0]
RTCCNTV
Rev. 1.00
power domain.
DD
Offset
RTC Counter Register
RTC Compare Register
RTC Control Register
RTC Status Register
RTC Interrupt and Wakeup Enable Register
30
29
28
22
21
20
0 RO
0 RO
14
13
12
0 RO
0 RO
6
5
0 RO
0 RO
Descriptions
RTC Counter Value
The current value of the RTC counter is returned when reading the RTCCNT register.
The RTCCNT register is updated during the falling edge of the CK_SECOND clock.
This register is reset by one of the following conditions:
- V
Domain software reset – set the PWCURST bit in the PWRCR register
DD
- V
Domain power on reset – POR
DD
- Compare match (RTCCNT = RTCCMP) when CMPCLR = 1 (in the RTCCR
register)
- RTCEN bit changed from 0 to 1
404 of 576
Description
27
26
Reserved
19
18
RTCCNTV
0 RO
0 RO
11
10
RTCCNTV
0 RO
0 RO
4
3
2
RTCCNTV
0 RO
0 RO
Reset Value
0x0000_0000
0x0000_0000
0x0000_0F00
0x0000_0000
0x0000_0000
25
24
17
16
0 RO
0 RO
0
9
8
0 RO
0 RO
0
1
0
0 RO
0 RO
0
January 28, 2022
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