Timer Interrupt Status Register - Intsr - Holtek HT32F54231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Timer Interrupt Status Register – INTSR
This register stores the timer interrupt status.
Offset: 0x07C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset
Bits Field
[10] TEVIF
[8] UEVIF
[4] CHOCF
[0] CHCCIF
Rev. 1.00
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
CHOCF
W0C
Descriptions
Trigger Event Interrupt Flag
This flag is set by hardware on a trigger event and is cleared by software.
0: No trigger event occurs
1: Trigger event occurs
Update Event Interrupt Flag
This bit is set by hardware on an update event and is cleared by software.
0: No update event occurs
1: Update event occurs
Note: The update event is derived from the following conditions:
- The counter overflows
- The UEVG bit is asserted
- A restart trigger event occurs from the slave trigger input
Channel Over-Capture Flag
This flag is set by hardware and cleared by software.
0: No over-capture event is detected
1: Capture event occurs again when the CHCCIF bit is already set and it is not
yet cleared by software.
Channel Capture/Compare Interrupt Flag
- Channel is configured as an output:
0: No match event occurs
1: The contents of the counter CNTR have matched the content of the CHCCR
register
This flag is set by hardware when the counter value matches the CHCCR value. It is
cleared by software.
- Channel is configured as an input:
0: No input capture occurs
1: Input capture occurs
This bit is set by hardware on a capture event. It is cleared by software or by reading
the CHCCR register.
390 of 576
27 26
Reserved
19 18
Reserved
11 10
TEVIF
W0C 0
3 2
Reserved
0
25 24
17 16
9 8
Reserved UEVIF
W0C 0
1 0
CHCCIF
W0C 0
January 28, 2022