B&R Automation PC 3100 User Manual page 165

BIOS parameter
CTO
SEFE
SENFE
SECE
PME SCI
Hot plug
Advanced error reporting
PCIe speed
Transmitter half swing
Detect timeout
Extra bus reserved
Reserved memory
Reserved I/O
PCH PCIe LTR configuration
PCH PCIE1 LTR
Snoop latency override
Snoop latency value
Snoop latency multiplier
Non-snoop latency override
Non-snoop latency value
Non-snoop latency multiplier
Force LTR override
PCIE1 LTR lock
PCH PCIe CLKREQ#
PCH PCIe CLKREQ# mapping override
CLKREQ number
1) PCI Express root port n must be enabled in order to make further configurations.
2) Upstream port transmitter preset
The default value is system-optimized by B&R.
3) Downstream port transmitter preset
The default value is system-optimized by B&R.
4) Changes to the ACS have no effect on the display of the following indented parameters.
Automation PC 3100 User's manual V 2.10
Setting options
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Auto
Gen1
Gen2
Gen3
Disabled
Enabled
INT
Default: 0
INT
Default: 0
INT
Default: 10
INT
Default: 4
Disabled
Enabled
Auto
Disabled
Manual
INT
Default: 60
1 ns
32 ns
1024 ns
32768 ns
1048576 ns
33554432 ns
Auto
Disabled
Manual
INT
Default: 60
1 ns
32 ns
1024 ns
32768 ns
1048576 ns
33554432 ns
Disabled
Enabled
Disabled
Enabled
Custom number
Default
No CLKREQ
INT
Default: 0
Table 110: Advanced - PCH-IO configuration - PCI Express root port n
Description
Notification of correctable errors
5)
Disables/Enables PCIe completion timer timeout
Disables/Enables system error on fatal error
Disables/Enables system error on non-fatal error
Disables/Enables system error on correctable error
Disables/Enables system control interrupt on a power management event
Disables/Enables hot plugging
Disables/Enables advanced error reporting
Selects the PCIe transfer rate [gigatransfers per second (GT/s)] automatically or manu-
ally
Gen1: Max. 2.5 GT/s
Gen2: Max. 5.0 GT/s
Gen3: Max. 8.0 GT/s
Disables/Enables transmitter half-swing
Signals are transferred with a half-swing.
Defines the detect timeout [ms]
If no link is received from an enabled port after the detect timeout has expired, it is as-
sumed that no device is present there. The system can disable the port if necessary.
Range: 0 to 65535
Defines the extra bus reserved for bridges after this root bridge
Range: 0 to 7
Defines reserved memory [MB] for this bridge
Range: 0 to 20
Defines the reserved I/O range for this bridge
Range: 4 to 20 kB
Resolution: 4 kB
Disables/Enables PCIe latency reporting
Disables the snoop latency override or selects manual or automatic mode
Defines the snoop latency value
Range: 0 to 1023
Defines the snoop latency multiplier value [ns]
Disables the non-snoop latency override or selects manual or automatic mode
Defines the non-snoop latency value
Range: 0 to 1023
Defines the non-snoop latency multiplier value [ns]
Disables/Enables force LTR override
Disables/Enables the PCIE1 LTR lock function
Disables the clock request number for standard platform mapping or uses the default
values or manual value
Defines the CLKREQ number
Range: 0 to 15
Software
6)
6)
6)
165