Figure 535. Usart_Ker_Ck Clock Divider Block Diagram - ST STM32G4 Series Reference Manual

Universal synchronous/asynchronous receiver transmitter (USART/UART)
Selecting the clock source and the appropriate oversampling method
The choice of the clock source is done through the Clock Control system (see Section Reset
and clock control (RCC)). The clock source must be selected through the UE bit before
enabling the USART.
The clock source must be selected according to two criteria:
•
Possible use of the USART in low-power mode
•
Communication speed.
The clock source frequency is usart_ker_ck.
When the dual clock domain and the wakeup from low-power mode features are supported,
the usart_ker_ck clock source can be configurable in the RCC (see Section Reset and clock
control (RCC)). Otherwise the usart_ker_ck clock is the same as usart_pclk.
The usart_ker_ck clock can be divided by a programmable factor, defined in the
USART_PRESC register.
usart_ker_ck
Some usart_ker_ck sources enable the USART to receive data while the MCU is in low-
power mode. Depending on the received data and wakeup mode selected, the USART
wakes up the MCU, when needed, in order to transfer the received data, by performing a
software read to the USART_RDR register or by DMA.
For the other clock sources, the system must be active to enable USART communications.
The communication speed range (specially the maximum communication speed) is also
determined by the clock source.
The receiver implements different user-configurable oversampling techniques (except in
synchronous mode) for data recovery by discriminating between valid incoming data and
noise. This enables obtaining the best a trade-off between the maximum communication
speed and noise/clock inaccuracy immunity.
The oversampling method can be selected by programming the OVER8 bit in the
USART_CR1 register either to 16 or 8 times the baud rate clock (see
Figure 537).
Depending on your application:
•
select oversampling by 8 (OVER8=1) to achieve higher speed (up to
usart_ker_ck_pres/8). In this case the maximum receiver tolerance to clock deviation is
reduced (refer to
page
• select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to clock
deviations. In this case, the maximum speed is limited to maximum
1608/2126

Figure 535. usart_ker_ck clock divider block diagram

USARTx_PRESC[3:0]
Section 37.5.8: Tolerance of the USART receiver to clock deviation on
1612)
usart_ker_ck_pres
RM0440 Rev 4
RM0440
USARTx_BRR register
and oversampling
MSv40855V1
Figure 536 and