Pin Control Register (Pcr) - Texas Instruments TMS320VC5501 Reference Manual

Pin Control Register (PCR)

12.8 Pin Control Register (PCR)
12-38 McBSP Registers
Each McBSP has one pin control register of the form shown in Figure 12−8.
Table 12−11 describes the bits of PCR. This I/O-mapped register enables you
to:
Allow the McBSP to enter a low-power mode when the idle instruction is
-
executed (IDLEEN, in conjunction with the PERI bit of ICR). For the
TMS320VC5503/5507/5509 and TMS320VC5510 devices, this capability
is provided in the PCR. On the TMS320VC5501 and TMS320VC5502
devices, this capability is provided in the Peripheral Idle Control Register
(PICR). For more information on the TMS320VC5501 implementation,
see the TMS320VC5501 Fixed-Point Digital Signal Processor Data
Manual (literature number SPRS206); for the TMS320VC5502
implementation, see the TMS320VC5502 Fixed-Point Digital Signal
Processor Data Manual (literature number SPRS166).
Specify whether McBSP pins can be used as general-purpose I/O pins
-
when the transmitter and/or receiver is in its reset state (XIOEN and
RIOEN)
Choose a frame-sync mode for the transmitter (FSXM) and for the receiver
-
(FSRM)
Choose a clock mode for transmitter (CLKXM) and for the receiver
-
(CLKRM)
Select the input clock source for the sample rate generator (SCLKME, in
-
conjunction with the CLKSM bit of SRGR2)
Read or write data when the CLKS, DX, and DR pins are configured as
-
general-purpose I/O pins (CLKSSTAT, DXSTAT, and DXSTAT)
Choose whether frame-sync signals are active low or active high (FSXP
-
for transmission, FSRP for reception)
Specify whether data is sampled on the falling edge or the rising edge of
-
the clock signals (CLKXP for transmission, CLKRP for reception)
SPRU592E