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4.7
Interrupt Raw Register (IRR)
The interrupt raw register (IRR) displays the raw status of the interrupt. If the interrupt condition occurs,
the corresponding bit in IRR is set independent of whether or not the interrupt is enabled. The IRR is
shown in
Figure 25
31
15
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Bit
Field
Value
31-3
Reserved
0
2
LT
0
1
1-0
Reserved
0
SPRUEM4A – November 2007
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and described in
Table
31.
Figure 25. Interrupt Raw Register (IRR)
Reserved
R-0
Table 31. Interrupt Raw Register (IRR) Field Descriptions
Description
Reserved
Line trap. Write a 1 to clear LT and the LTM bit in the interrupt masked register (IMR); a write of 0 has
no effect.
A line trap condition has not occurred.
Illegal memory access type. See
Reserved
Reserved
R-0
Section 2.14
for more details.
DDR2 Memory Controller Registers
3
2
1
LT
Reserved
R/W1C-0
R-0
DDR2 Memory Controller
16
0
49
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