Sensor Mode (Timer Count) And Timer Mode; Figure 3.23 Counter Configuration (Sensor Mode (Timer Count) And Timer Mode) - Toshiba TXZ Series Reference Manual

3.3.3.2. Sensor Mode (Timer Count) and Timer Mode

32-bit
counter
fsys
CLK
[ENxTNCR]
<MODE[0]>
ENCLK
From
ZDETECT
Decoder

Figure 3.23 Counter configuration (Sensor mode (Timer count) and Timer mode)

This circuit consists of a 32-bit counter operating with the system clock (fsys), 3 comparison function circuits
([ENxRELOAD], [ENxINT], and [ENxMCMP]), and a capture function circuit.
A match comparison and a magnitude comparison can be selected in MCMP comparison function. In the
magnitude comparison ([ENxTNCR]<MCMPMD>=1), the comparison starts at the setting of [ENxMCMP]
register and finishes when the condition is met and the MCMP met signal is generated.
In the timer mode, INT comparison or RELOAD comparison can clear the counter.
In the sensor mode (Timer count), the rotation edge detection (ENCLK) captures the counter value and clears the
counter. In the timer mode, Z edge detection (ZDETECT) can capture the counter value and clear the counter. The
captured value can be acquired by reading the counter register ([ENxCNT]).
When [ENxINTCR]<MCMPIE>=1 is set, MCMP comparison match signal can be used as the commutation
trigger for PMD circuit.
2018-10-11
[ENxMCMP]
[ENxINT]
CNT
[ENxTNCR]
<CMPSEL>
0
1
Clear
[ENxRELOAD]
[ENxTNCR]
<ENCLR> Write
0
1
Advanced Encoder Input Circuit(32-bit)
[ENxTNCR] [ENxINTCR]
<MCMPMD> <MCMPIE>
Magnitude
comparison
Match
comparison
Match
comparison
Capture
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TXZ Family
Commutation trigger
CTRGO To PMD
MCMP is met
INT match
RELOAD match
[ENxCNT]
Read
Capture trigger
Rev. 1.1