Bit Configuration; Figure 3.8 Can Bit Timing - Toshiba TXZ Series Reference Manual

3.5. Bit Configuration

The length of a bit is determined by the parameters [CANBCR2]<TSEG1>, [CANBCR2]<TSEG2>, and
[CANBCR1]<BRP>. All controllers on the CAN bus must have the same baud rate and bit length. At different
clock frequencies of the individual controllers, the baud rate has to be adjusted by the above-mentioned
parameters. In the bit timing logic, the conversion of the parameters to the required bit timing is implemented. The
configuration registers [CANBCR1] and [CANBCR2] contain the data about bit timing. Its definition corresponds
to the CAN specification 2 (equivalent to Intel 82527).
Figure 3.8 shows CAN bit timing.
SYNCSEG
[CANBCR2]
<SJW>
T (CAN system clock) is defined by:
SCL
1 × T = 1 × T (T
SCL Q
f is the clock for CAN baud rate generation. The clock obtained by dividing the system clock f
CANOSC
supplied as the clock for CAN baud rate generation. If f
The synchronization segment SYNCSEG always has the length of one T
The baud rate is defined by:
BR=
(([CANBCR2]<TSEG1[3:0]>+1)+([CANBCR2]<TSEG2[2:0]>+1)+1)×T
Note: It is not T unit value.
Q
2018-10-30
[CANBCR2]<TSEG1>

Figure 3.8 CAN Bit Timing

[CANBCR1]<BRP[9:0]>+1
T =
SCL
: time quantum )
Q
1 bit time(TBIT)
Sample point
f
CANOSC
= 40MHz then f
SYS CANOSC
.
Q
1
25 / 54
TXZ Family
CAN Controller
[CANBCR2]
<SJW>
[CANBCR2]<TSEG2>
IPT
by 4 is
SYS
= 10MHz.
SCL
Rev. 1.1