The Peripheral Function State In A Low Power Consumption Mode; Table 1.10 Block Operation Status In Each Low Power Consumption Mode - Toshiba TXZ+ Series Reference Manual

1.3.1.4. The peripheral function state in a Low Power Consumption mode

The following Table 1.10 shows the Operation State of the peripheral function (block) in each mode.
In addition, after reset release, it will be in the state where a clock is not supplied except for some blocks.
If needed, set up [CGFSYSENA], [CGFSYSMENA], [CGFSYSMENB], [CGFCEN], [CGSPCLKEN] and
enable clock supply.

Table 1.10 Block operation status in each Low Power Consumption mode

Processor core (Including Debug)
DMAC
I/O port
ADC (with OPAMP)
UART
I2C
EI2C
TSPI
A-PMD
A-ENC32
A-VE+
T32A
TRGSEL
CRC
SIWDT
LVD
OFD
TRM
CG
PLL
RAMP
External High speed oscillator (EHOSC)
Internal High speed oscillator1 (IHOSC1)
Internal High speed oscillator2 (IHOSC2)
Code Flash
Data Flash
RAM
: Operation is possible.
-: If it shifts to the object mode, the clock to peripheral circuits stop automatically.
Note1: Protect A mode only. In other cases, stop SIWDT before transiting to IDLE mode.
Note2: It becomes a data hold when peripheral functions (DMA etc.) except CPU which carry out
data access (R/W) are not connected on the bus matrix.
Block
Pin status
Register
24 / 64
Clock Control and Operation Mode
NORMAL IDLE
-

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 (Note1)

 
 
Unavailable

 
 
 
 
 
 
Access
Access
Possible
Possible
(Note2)
TXZ+ Family
TMPM4K Group(2)
STOP1
-
-

-
-
-
-
-
-
-
-
-
-
-
-
-

-
-

-
-
-
-
-
Data
hold
2021-06-15
Rev. 1.1