Specific Masks And Factor Flags For Interrupt - Epson S1C6S3N2 Technical Manual

Specific masks and
factor flags for inter-
rupt
Table 4.13.2
Interrupt mask registers and
interrupt factor flags
S1C6S3N2 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
The interrupt factor flags can be masked by the correspond-
ing interrupt mask registers.
The interrupt mask registers are read/write registers. They
are enabled (interrupt authorized) when "1" is written to
them, and masked (interrupt inhibited) when "0" is written
to them.
At initial reset, the interrupt mask register is set to "0".
Table 4.13.2 shows the correspondence between interrupt
mask registers and interrupt factor flags.
Interrupt Mask Register
ETI2 (078H·D2)
ETI8 (078H·D1)
ETI32 (078H·D0)
EISWIT1 (076H·D1)
EISWIT0 (076H·D0)
EIK03 (075H·D3)
EIK02 (075H·D2)
EIK01 (075H·D1)
EIK00 (075H·D0)
EIK10 (077H·D2)
* There is an interrupt mask register for each pin
of the input ports.
EPSON
Interrupt Factor Flag
TI2 (079H·D2)
TI8 (079H·D1)
TI32 (079H·D0)
SWIT1 (07AH·D1)
SWIT0 (07AH·D0)
(07AH·D2)
IK0
IK1 (07AH·D3)
I-91