Table 2-1. Host Interface Reset And S3 States - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

R

Table 2-1. Host Interface Reset and S3 States

Interface Signal Name
Host I/F HCPURST#
HADSTB[1:0]#
HA[31:3]#
HD[63:0]
HDSTBP[3:0]#
HDSTBN[3:0]#
HDINV[3:0]#
HADS#
HBNR#
HBPRI#
HDBSY#
HDEFER#
HDRDY#
HEDRDY#
Host I/F HHIT#
HHITM#
HLOCK#
HREQ[4:0]#
HTRDY#
HRS[2:0]#
HBREQ0#
HPCREQ#
HVREF
HRCOMP
HSWING
HSCOMP
®
Intel 82925X/82925XE MCH Datasheet
State During
I/O RSTIN#
Assertion
O DRIVE LV TERM HV after
approximately 1ms
I/O TERM HV
I/O TERM HV
I/O TERM HV
I/O TERM HV
I/O TERM HV
I/O TERM HV
I/O TERM HV
I/O TERM HV
O TERM HV
I/O TERM HV
O TERM HV
I/O TERM HV
O TERM HV
I/O TERM HV
I/O TERM HV
I/O TERM HV
I/O TERM HV
O TERM HV
O TERM HV
I/O TERM HV
I TERM HV
I IN
I/O TRI TRI after RCOMP
I IN
I/O TRI
State After S3
RSTIN# De-
assertion
TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
TERM HV TRI (No VTT)
IN TRI
TRI
IN
TRI TRI
Signal Description
Pull-up/
Pull-down
20 Ω resistor
for board with
target
impedance of
60 Ω
31