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Philips Semiconductors
3.2.6 Clock divider
The A/D converter requires that its internal clock source be in the range of 320 kHz to
9 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to
8 is provided for this purpose (See
3.2.7 I/O pins used with ADC functions
The analog input pins maybe be used as either digital I/O or as inputs to A/D and thus
have a digital input and output function. In order to give the best analog performance, pins
that are being used with the ADC should have their digital outputs and inputs disabled and
have the 5V tolerance disconnected. Digital outputs are disabled by putting the port pins
into the input-only mode as described in the Port Configurations section (see
Digital inputs will be disconnected automatically from these pins when the pin has been
selected by setting its corresponding bit in the ADINS register and its corresponding A/D
has been enabled
When used as digital I/O these pins are 5 V tolerant. If selected as input signals in ADINS,
these pins will be 3V tolerant if the corresponding A/D is enabled and the device is not in
power down. Otherwise the pin will remain 5V tolerant. Please refer to the P89LPC938
data sheet for specifications.
3.2.8 Power-down and Idle mode
In Idle mode the A/D converter, if enabled, will continue to function and can cause the
device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled.
In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is
enabled, it will consume power. Power can be reduced by disabling the A/D.
Table 11:
A/D Control register 0 (ADCON0 - address 97h) bit allocation
Bit
7
Symbol
ENBI0
Reset
0
Table 12:
A/D Control register 0 (ADCON0 - address 97h) bit description
Bit
Symbol
1:0
ADCS01,ADCS00 A/D start mode bits, see below.
2
ENADC0
3
ADCI0
4
EDGE0
User manual
6
5
ENADCI0
TMM0
0
0
Description
00 — Timer Trigger Mode when TMM0 = 1. Conversions starts on overflow of Timer
0. When TMM0 =0, no start occurs (stop mode).
01 — Immediate Start Mode. Conversion starts immediately.
10 — Edge Trigger Mode. Conversion starts when edge condition defined by bit
EDGE0 occurs.
Enable ADC0. When set = 1, enables ADC0, when = 0, the ADC is in power-down.
A/D Conversion complete Interrupt 0. Set when any conversion or set of multiple
conversions has completed. Cleared by software.
An edge conversion start is triggered by a falling edge on P1.4 when EDGE0 =0
while in edge-triggered mode. An edge conversion start is triggered by a rising edge
on P1.4 when EDGE0 =1 while in edge-triggered mode.
Rev. 03 — 7 June 2005
Table
16).
4
3
EDGE0
ADCI0
0
0
UM10119
P89LPC938 User manual
2
1
ENADC0
ADCS01
0
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table
24).
0
ADCS00
0
27 of 139
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