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Philips Semiconductors
General Description
Memory organization
The P89LPC920/921/922 memory map is shown in Figure 1-1.
FF00h
IAP entry-points
FFEFh
1FFFh
ISP CODE (512B)*
1E00h
Sector 7
1C00h
1BFFh
Sector 6
1800h
17FFh
Sector 5
1400h
13FFh
Sector 4
1000h
0FFFh
Sector 3
0C00h
0BFFh
Sector 2
0800h
07FFh
Sector 1
0400h
03FFh
Sector 0
0000h
The various P89LPC920/921/922 memory spaces are as follows:
DATA
128 bytes of internal data memory space (00h..7Fh) accessed via direct or indirect addressing, using instructions
other than MOVX and MOVC. All or part of the Stack may be in this area.
IDATA
Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via indirect addressing using
instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA
area and the 128 bytes immediately above it.
SFR
Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via
direct addressing.
CODE
64 KB of Code memory space, accessed as part of program execution and via the MOVC instruction. The
P89LPC920/921/922 has 2 KB/ 4 KB/ 8 KB of on-chip Code memory.).
2003 Dec 8
Read-protected
IAP calls only
IAP routines
entry points for:
- 51 ASM. code
-
C code
ISP
serial loader
-
UART (auto-baud)
- I2C, SPI etc. *
Flexible choices:
- as supplied (UART)
*
- Philips libraries
- user-defined
Note: ISP code is located at the end of Sector
1 on the LPC920, at the end of Sector 4 on the
LPC921, AND AT THE END OF Sector 7 on
the LPC922.
Figure 1-1: P89LPC920/921/922 memory map
18
FFEFh
Special Function
Registers
(directly addressable)
FF1Fh
entry points
FF00h
1FFFh
1E00h
User's Manual - Preliminary -
P89LPC920/921/922
IDATA (incl. DATA)
128 Bytes On-Chip
Data Memory (stack
and indirect addr.)
DATA
128 Bytes On-Chip
Data Memory (stack,
direct and indir. addr.)
4 Reg. Banks R0-R7
Data Memory
(DATA, IDATA)
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