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Philips Semiconductors
Fig 31. I
The P89LPC938 CPU interfaces with the I
(SFRs): I2CON (I
Register), I2ADR (I
Byte), and I2SCLL (SCL Duty Cycle Register Low Byte).
2
12.1 I
I2DAT register contains the data to be transmitted or the data received. The CPU can read
and write to this 8-bit register while it is not in the process of shifting a byte. Thus this
register should only be accessed when the SI bit is set. Data in I2DAT remains stable as
long as the SI bit is set. Data in I2DAT is always shifted from right to left: the first bit to be
transmitted is the MSB (bit 7), and after a byte has been received, the first bit of received
data is located at the MSB of I2DAT.
Table 73:
Bit
Symbol
Reset
12.2
I
I2ADR register is readable and writable, and is only used when the I
slave mode. In master mode, this register has no effect. The LSB of I2ADR is general call
bit. When this bit is set, the general call address (00h) is recognized.
Table 74:
Bit
Symbol
Reset
Table 75:
Bit Symbol
0
1:7 I2ADR1:7 7 bit own slave address. When in master mode, the contents of this register has
User manual
2
I
C-bus
P1.3/SDA
P89LPC932A1
2
C-bus configuration.
2
C Control Register), I2DAT (I
2
C Slave Address Register), I2SCLH (SCL Duty Cycle Register High
C data register
2
I
C data register (I2DAT - address DAh) bit allocation
7
6
I2DAT.7
I2DAT.6
0
0
2
C slave address register
2
I
C slave address register (I2ADR - address DBh) bit allocation
7
6
I2ADR.6
I2ADR.5
0
0
2
I
C slave address register (I2ADR - address DBh) bit description
Description
GC
General call bit. When set, the general call address (00H) is recognized,
otherwise it is ignored.
no effect.
Rev. 03 — 7 June 2005
R
R
P
P
OTHER DEVICE
P1.2/SCL
2
WITH I
C-BUS
INTERFACE
2
C-bus through six Special Function Registers
2
C Data Register), I2STAT (I
5
4
3
I2DAT.5
I2DAT.4
I2DAT.3
0
0
0
5
4
3
I2ADR.4
I2ADR.3
I2ADR.2
0
0
0
UM10119
P89LPC938 User manual
SDA
SCL
OTHER DEVICE
2
WITH I
C-BUS
INTERFACE
002aaa898
2
C Status
2
1
0
I2DAT.2
I2DAT.1
I2DAT.0
0
0
0
2
C interface is set to
2
1
0
I2ADR.1
I2ADR.0
GC
0
0
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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