Sre Service Request Enable Register - Fluke Calibration 5322A Operator's Manual

5322A
Operators Manual
Status data structure contains following registers:
STB – Status Byte Register
SRE – Service Request Enable Register
ESR – Event Status Register
ESE – Event Status Enable Register
Output Queue
STB Status Byte Register
STB is the main register where information from other status registers and from
output queue is collected. Value of STB register is reset after switching on the
Product or after sending command *CLS. This command reset the STB register
except bit MAV, which remains set if the output queue is not empty. STB register
value can be read via serial message or through general query *STB?. See
Table 18.
Bit Name
OSS
RQS
MSS
ESB
MAV
QSS

SRE Service Request Enable Register

The Service Request Enable Register suppresses or allows the STB bits. 0 value
of a SRE bit means, that the bit does not influence value of MSS bit. Value of any
unmask STB bit results in setting of the MSS bit to the level 1. SRE bit 6 is not
influenced and its value is 0. The SRE register value can be set via the command
*SRE followed by mask register value (0 – 191). The register can be read with
the command *SRE?. The register is automatically resets after switching the
Product on. The register is not reset by the command *CLS.
152
Table 18. Bit Configuration of the Status Byte Register
Operation Summary Status, bit 7. SCPI-defined. The OSS bit is set to 1 when
the data in the OSR (Operation Status Register) contains one or more enabled
bits which are true.
Request Service, bit 6. The bit is read as a part of status byte only when serial
message is sent.
Master Summary Status, bit 6. The MSS bit is set to 1 whenever bits ESB or
MAV are 1 and enabled (1) in the SRE. This bit can be read using the *STB?
command. His value is derived from STB and SRE status.
Event Summary Bit, bit 5. His value is derived from STB and SRE status. The
ESB bit is set to 1 when one or more enabled ESR bits are set to 1.
Message Available, bit 4. The MAV bit is set to 1 whenever data is available in
the IEEE488 Output Queue (the response on query is ready).
Questionable Summary Status, bit 3. SCPI-defined. The QSS bit is set to 1
when the data in the QSR (Questionable Status Register) contains one or more
enabled bits which are true.
Description