Bus Block Diagram - Freescale Semiconductor 56F800 User Manual

PLL
Clock
Generator
Internal
Data Bus
Switch
It is possible in a single instruction cycle for the program controller to be fetching a first
instruction, the AGU to generate two addresses for a second instruction, and the Data ALU to
perform a multiply in a third instruction. In a similar manner, the Bit Manipulation Unit (BMU)
can perform an operation of the third instruction previously described instead of the
multiplication in the Data ALU. The architecture is pipelined to take advantage of the parallel
units and significantly decrease the execution time of each instruction.
Freescale Semiconductor
Program
RAM/FLASH
Expansion
XAB1
Address
XAB2
Generation
PAB
Unit
PDB
CGDB
Program
Controller
IRQB
IRQA
RESET
Figure 1-2. 56800 Bus Block Diagram
56F826/827 Overview, Rev. 3
Data
RAM/FLASH
Expansion
16-Bit
Core
Data ALU
→
16 x 16 + 36 36-Bit Mac
Three 16-Bit Input Regs
Two 36-Bit Accumulators
16 Bit Data Bus
56800 Core Description
On-Chip
Expansion
Area
Peripheral
Modules
IPBus
Bridge
TM
OnCE
7