Fast Data - Freescale Semiconductor 56F800 User Manual

Functional Description
10-bit × 16 RT cycles + 10 RT cycles = 170 RT cycles
With the misaligned character illustrated in
point when the count of the transmitting device is:
10-bit × 16 RT cycles + 3 RT cycles = 163 RT cycles
The maximum percentage difference between the receiver count and the transmitter count of a
slow 9-bit character with no errors is:
10.4.4.5.2 Fast Data Tolerance
Figure 10-7 illustrates how much a fast received frame can be misaligned without causing a
noise error or a framing error. The fast STOP bit ends at RT10 instead of RT16 but it is still
sampled at RT8, RT9, and RT10.
Receiver
RT Clock
For an 8-bit (all 0s or 1s) data character, data sampling of the STOP bit takes the receiver:
9-bit × 16 RT cycles + 10 RT cycles = 154 RT cycles
With the misaligned character, illustrated in
the point when the count of the transmitting device is:
The maximum percentage difference between the receiver count and the transmitter count of a
fast 8-bit character with no errors is:
14
154 - 147
×
100
---------------------- -
154
Figure
170 -163
×
100
---------------------
170
STOP
Figure 10-7. Fast Data
Figure
10-bit × 16 RT cycles = 160 RT cycles
154 -160
×
100
---------------------
154
56F826/827 User Manual, Rev. 3
= 4.54%
10-6, the receiver counts 170 RT cycles at the
= 4.12%
Idle or Next Frame
Data
Samples
10-7, the receiver counts 154 RT cycles at
= 3.90%
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