Freescale Semiconductor CPU32 Manuals

Manuals and User Guides for Freescale Semiconductor CPU32. We have 1 Freescale Semiconductor CPU32 manual available for free PDF download: Reference Manual

Freescale Semiconductor CPU32 Reference Manual

Freescale Semiconductor CPU32 Reference Manual (330 pages)

Brand: Freescale Semiconductor | Category: Controller | Size: 2 MB

Table of Contents

Table of Contents
5
Features
15
- Virtual Memory
  16
- Loop Mode Instruction Execution
  16
- Vector Base Register
  17
- Exception Handling
  17
- Enhanced Addressing Modes
  18
- Instruction Set
  18
  - Low-Power Stop Instruction
    20
- Processing States
  20
- Privilege States
  20
Section 1 Overview
15
Block Diagram
20
CPU32 Block Diagram
21
- Section 2Architecture Summary
  23
Programming Model
23
Registers
24
Data Types
25
- Organization in Registers
  26
  - Data Registers
    26
  - Address Registers
    27
  - Control Registers
    27
- Organization in Memory
  28
Memory Operand Addressing
29
- Section 3 Data Organization and Addressing Capabilities
  31
Program and Data References
31
Implicit Reference
32
Notation Conventions
32
Effective Address
33
Programming View of Addressing Modes
41
- Addressing Capabilities
  41
Using SIZE in the Index Selection
42
Addressing Array Items
43
- General Addressing Mode Summary
  44
M68000 Family Addressing Capability
44
Other Data Structures
45
- System Stack
  45
- User Stacks
  46
- Queues
  47
  - Section 4 Instruction Set
    49
M68000 Family Compatibility
49
- New Instructions
  49
  - Low-Power Stop (LPSTOP)
    49
- Unimplemented Instructions
  50
Instruction Format
50
- Table Lookup and Interpolation (TBL)
  50
- Notation
  51
Instruction Summary
53
- Condition Code Register
  53
- Data Movement Instructions
  54
- Integer Arithmetic Operations
  55
- Logic Instructions
  56
- Shift and Rotate Instructions
  57
- Bit Manipulation Instructions
  57
- Binary-Coded Decimal (BCD) Instructions
  58
- Program Control Instructions
  58
- System Control Instructions
  59
- Condition Tests
  60
Instruction Details
61
Instruction Description Format
62
Instruction Format Summary
218
State Transitions
243
- Supervisor Privilege Level
  244
Types of Address Space
245
- Type 0000 — Breakpoint
  246
- Type 1111 — Interrupt Acknowledge
  247
Definition of Exception Processing
249
- Types of Exceptions
  250
- Exception Processing Sequence
  251
- Multiple Exceptions
  252
Processing of Specific Exceptions
253
- Bus Error
  254
- Address Error
  255
- Instruction Traps
  256
- Format Error
  257
- Privilege Violations
  258
- Tracing
  259
- Interrupts
  260
- Return from Exception
  261
Fault Recovery
262
- Types of Faults
  264
- Normal Four-Word Stack Frame
  270
Internal Transfer Count Register
271
Format $C — BERR Stack for Prefetches and Operands
272
CPU32 Integrated Development Support
273
- Deterministic Opcode Tracking Overview
  274
- On-Chip Hardware Breakpoint Overview
  275
- Enabling BDM
  276
  - Double Bus Fault
    277
- Background Mode Registers
  278
  - Current Instruction Program Counter (PCC)
    279
  - CPU Serial Logic
    280
Serial Interface Timing Diagram
281
- Development System Serial Logic
  282
- Command Set
  283
  - Command Sequence Diagram
    284
Command-Sequence-Diagram Example
285
- Command Set Summary
  286
- Read A/D Register (RAREG/RDREG)
  287
- Read System Register (RSREG)
  288
- Read Memory Location (READ)
  289
- Write Memory Location (WRITE)
  290
- Dump Memory Block (DUMP)
  291
- Fill Memory Block (FILL)
  293
- Resume Execution (GO)
  294
- Reset Peripherals (RST)
  296
- Future Commands
  297
Functional Model of Instruction Pipeline
298
- Opcode Tracking During Loop Mode
  299
Resource Scheduling
301
Instruction Pipeline
302
- Prefetch Controller
  303
- Instruction Execution Overlap
  304
- Effects of Wait States
  305
- Effects of Negative Tails
  306
Instruction Stream Timing Examples
307
- Timing Example 2: Branch Instructions
  308
- Timing Example 3: Negative Tails
  309
Instruction Timing Tables
310
- Fetch Effective Address
  312
- Calculate Effective Address
  313
MOVE Instruction
314
Arithmetic/Logic Instructions
315
Immediate Arithmetic/Logic Instructions
317
Binary-Coded Decimal and Extended Instructions
318
Shift/Rotate Instructions
319
- Bit Manipulation Instructions
  320
Control Instructions
321
Save and Restore Operations
322

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