Register Summary; Gpio Interrupt Assert Functionality; Gpio Registers With Reset Values - Freescale Semiconductor 56F800 User Manual

The eight (or 16 in GPIO port A and G on the 56F827) interrupt signals are read together to
present only a single interrupt to the core. The interrupt service routine must then check the
contents of the interrupt pending register, determining which pin(s) caused the interrupt.
External interrupt sources do not need to remain asserted due to the edge sensitive nature of the
detection mechanism.
IPOLR Interrupt Asserted
0
1

8.6 Register Summary

Each GPIO module has nine, 8-bit registers or 16-bit registers. They are provided in
Register Description
PUR Pull-up Enable Register
DR Data Register
DDR Data Direction Register
PER Peripheral Enable Register
IAR Interrupt Assert Register
IENR Interrupt Enable Register
IPOLR Interrupt Polarity Register
GPIO_IPR Interrupt Pending Register
Interrupt Edge Sensitive
IESR
Register
Table 8-4 illustrates the state of the PAD and pull-up resistor.
Freescale Semiconductor
Table 8-2. GPIO Interrupt Assert Functionality
If the IENR is set to one, as the pin goes to high, an interrupt will be
High
recorded by the GPIO_IPR register.
If the IENR is set to one, as the pin goes to low, an interrupt will be
Low
recorded by the GPIO_IPR register.
Table 8-3. GPIO Registers With Reset Values
Binary Reset
State for
Lower 8 bits
$11111111
$00000000
$00000000
$11111111
$00000000
$00000000
$00000000
$00000000
$00000000
General Purpose Input/Output (GPIO), Rev. 3
Remark
Remark
Pull-ups are enabled. (Please see
DR is used for data interface between the pin and
the IP Bus.
GPIO is set to an input. If DDR is one the GPIO
becomes an output.
Peripheral controls the GPIO. The DDR register
does not determine the direction of the I/O.
No interrupt.
Interrupt is disabled.
When set to one, the interrupts are active low. When
set to zero, interrupts are active high.
No interrupt is registered. A one indicates an
interrupt.
A one indicates an edge has been detected.
Register Summary
Table 8-3.
Table 8-4.)
9