Register Definitions; Spi Memory Map - Freescale Semiconductor 56F800 User Manual

16-bit digital signal controllers
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Register Definitions

11.7.2.2 Slave SPI Mode Fault
In a slave SPI (SPMSTR = 0), the MODF bit generates a SPI Receiver/Error Interrupt request if
the ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way.
Software can abort the SPI transmission by clearing the SPE bit of the slave.
Note:
A Logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance
state. Also, the slave SPI ignores all incoming SCLK clocks, even if it was already in
the middle of a transmission.
When configured as a slave (SPMSTR = 0), the MODF flag is set if the SS goes high during a
transmission. When CPHA = 0, a transmission begins when SS goes low and ends once the
incoming SCLK goes back to its idle level, following the shift of the last data bit. When CPHA =
1, the transmission begins when the SCLK leaves its idle level and SS is already low. The
transmission continues until the SCLK returns to its idle level following the shift of the last data
bit.
To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPSCR.
This entire clearing mechanism must occur with no MODF condition existing or else the flag is
not cleared.
In a slave SPI, if the MODF flag is not cleared by writing a one to the MODF bit, the condition
causing the Mode Fault still exists. In this case, the interrupt caused by the MODF flag can be
cleared by disabling the EERIE or MODFEN bits (if set) or by disabling the SPI. Disabling the
SPI using the SPE bit will cause a partial reset of the SPI and may cause the loss of a message
currently being received or transmitted.
11.8 Register Definitions
Table 11-2
lists the SPI registers in ascending address, including their acronyms and address of
each register. The read/write registers should be accessed only with word accesses. Accesses
other than word lengths result in undefined results.
registers.
18
Table 11-1. SPI Memory Map
Device
Peripheral
SPI0_BASE
82x
SPI1_BASE
56F826/827 User Manual, Rev. 3
Address
$1140
$1150
Figure 11-10
portrays a map summary of the
Freescale Semiconductor

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