Pin Descriptions; Jtag Pin Descriptions - Freescale Semiconductor 56F800 User Manual

Pin Descriptions

• Sample the system pins during operation and transparently shift-out the result in the BSR;
pre-load values to output pins prior to invoking the EXTEST instruction
• Disable output drive to pins during circuit board testing
• Provide means of accessing the OnCE module controller and circuits to control a target
system
• Query identification information, manufacturer, part number, and version from chip
• Force test data onto the outputs of an Integrated Circuit (IC) while replacing its BSR in the
serial data path with single bit register
• Enable weak pull-up current device on all input signals of an IC, helping to assure
deterministic test results in the presence of continuity fault during interconnect testing
Aspects of the JTAG implementation presented here are specific to the 56F826/827. For internal
details and applications of the standard, refer to IEEE 1149.1a.
17.3 Pin Descriptions
As described in IEEE 1149.1a, the JTAG port requires a minimum of four pins to support TDI,
TDO, TCK, and TMS signals. The 56F826/827 also uses the optional TRST input signal and DE
output signal used by the OnCE module interface. The pin functions are described in
Pin Name
TDI Test Data Input—This input pin provides a serial input data stream to the JTAG and the OnCE
module. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.
TDO Test Data Output—This tri-state output pin provides a serial output data stream from the JTAG and
the OnCE module. It is driven in the Shift-IR and Shift-DR controller states of the JTAG state
machine and changes on the falling edge of TCK.
TCK Test Clock Input—This input pin provides a gated clock to synchronize the test logic and shift serial
data to and from the JTAG/OnCE port. If the OnCE module is not being accessed, the maximum
TCK frequency is 1/4 the maximum freqency for the 56800 core. When accessing the OnCE module
through the JTAG TAP, the maximum frequency for TCK is 1/8 the maximum frequency specified
for the 56800 core . The TCK pin has an on-chip pull-down resistor.
TMS Test Mode Select Input—This input pin is used to sequence the JTAG TAP controller's state
machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.
Test Reset—This input provides a reset signal to the JTAG TAP controller. The operational mode
TRST of the pin is configured by Bit 14 of the OnCE Control Register (OCR). The TRST pin has an on-chip
pull-up resistor.
DE Debug Event—This output signal debugs events detected on a trigger condition.
4
Table 17-1. JTAG Pin Descriptions
Pin Description
56F826/827 User Manual, Rev. 3
Table 17-1.
Freescale Semiconductor