Mode Fault Error - Freescale Semiconductor 56F800 User Manual

11.7.2 Mode Fault Error

Setting the SPMSTR bit selects Master mode, configuring the SCLK and MOSI pins as outputs
and the MISO pin as an input. Clearing SPMSTR selects Slave mode, configuring the SCLK and
MOSI pins as inputs and the MISO pin as an output. The Mode Fault (MODF) bit becomes set
any time the state of the SS pin is inconsistent with the mode selected by SPMSTR. To prevent
SPI pin contention and damage to the 16-bit controller, a Mode Fault Error occurs if:
• The SS pin of a slave SPI goes high during a transmission.
• The SS pin of a master SPI goes low at any time.
To set the MODF flag, Mode Fault Error Enable (MODFEN) bit must be set. Clearing the
MODFEN bit does not clear the MODF flag but it does prevent the MODF from being set again
after the MODF is cleared.
MODF generates a receiver/error interrupt request if the Error Interrupt Enable (ERRIE) bit is
also set. It is not possible to enable MODF or OVRF individually to generate a receiver/error
interrupt request. However, leaving MODFEN low prevents MODF from being set.
11.7.2.1 Master SPI Mode Fault
In a master SPI with Mode Fault Enable (MODFEN) bit set, Mode Fault (MODF) flag is set if SS
goes to Logic 0. A Mode Fault in a Master SPI causes the following events to occur:
• If ERRIE = 1, the SPI generates a SPI receiver/error interrupt request.
• The SPE bit is cleared
• The SPTE bit is set
• The SPI state counter is cleared
In a master SPI, the MODF flag will not be cleared until the SS pin is at a Logic 1 or the SPI is
configured as a slave.
Note: When CPHA = 0, a MODF occurs if a slave is selected (SS is at Logic 0) and later
unselected (SS is at Logic 1) even if no SCLK is sent to that slave. This happens
because SS at Logic 0 indicates the start of the transmission (MISO driven out with the
value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later
unselected with no transmission occurring. Therefore, MODF does not occur since a
transmission was never begun.
Freescale Semiconductor
Serial Peripheral Interface (SPI), Rev. 3
Error Conditions
17