Freescale Semiconductor 56F800 User Manual page 583

Application:
TMR
arch.h: ArchIO.TimerA.Channel i.StatusControlReg
registers.h: ArchIO_TimerA_Channel i_StatusControlReg
Where i = 0, 1, 2, or 3
External Input Signal
External input pin polarity is unchanged
External input pin polarity is inverted
Input Capture Mode
Capture Mode specifies the operation of the Capture
Register, CAP, and the Input Edge Flag, IEF.
The Capture function is disabled, and the
Input Edge Flag interrupts are disabled
Load the Capture register on a rising
Load the Capture register on a falling
Load the Capture register on both input
Master Mode
Enable External OFLAF Force
Compare disabled
Enables a compare from another
Bits
TMR Status and
Read
Control Registers
Write
(SCR)
Reset
TMR_BASE +$7, $F, $17, or $1F
TMRA0_SCR (Timer A, Channel 0 Status & Control)—Address: TMRA_BASE + $7
TMRA1_SCR (Timer A, Channel 1 Status & Control)—Address: TMRA_BASE + $F 56F826 – $17 56F827
TMRA2_SCR (Timer A, Channel 2 Status & Control)—Address: TMRA_BASE + $17 56F826 – $27 56F827
TMRA3_SCR (Timer A, Channel 3 Status & Control)—Address: TMRA_BASE + $1F 56F826 – $37 56F827
Reserved Bits
Freescale Semiconductor
TMR Status and Control Registers (SCR) Continued
INPUT
0
1
CAPTURE
MODE
00
01
input edge
10
input edge
11
edges
MSTR
Disabled 0
Enabled 1
EEOF
0
1
counter/timer
15 14 13 12 11 10
TCF TCFIE TOF TOFIE IEF IEFIE IPS
0 0 0 0 0
Appendix B - Programmer's Sheets, Rev. 3
VAL
0 VAL is disabled
VAL initiates a read of teh OFLAG output
signal value when a FORCE command is
1 triggered by software or when a FORCE
command is issued by a counter/timer
set as a master.
FORCE
0 This bit always reads as zero.
Forces the current value of the VAL bit to
be written to the OFLAG output. (FORCE
and VAL bits can be written in a single
write operation.)
1
Note: Write to the FORCE bit only if the
counter is disabled. Setting this bit
while the counter is enabled may
yield unpredicable results.
OPS
0 True polarity
1 Inverted polarity
OEN
0 OFLAG output signal is disabled
Enable the OFLAG output signal to be
1 put on the external pin. Also connects a
timer's output pin to its input.
9 8 7 6 5
INPUT CAPTURE
MSTR EEOF VAL
MODE
0 0 0 0 0 0
Date:
Programmer:
5 of 14
Sheet
Forced OFLAG Value
Force the OFLAG Output
Output Polarity Select
Output Enable
4 3 2 1 0
0
OPS OEN
FORCE
0 0 0 0 0
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