Frame Sync And Clock Pin Configuration - Freescale Semiconductor 56F800 User Manual

SSI_RCK_OUT pin, and an external clock source can drive this pin to clock the RXSR.
12-4 defines the clock pin configuration.
Note: RXDIR and SYN must both be set for the SSI to be in gated clock mode.
Table 12-14. Frame Sync and Clock Pin Configuration
SYN RXDIR
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
12.4.8.8 Transmit Clock Direction (TXDIR) - Bit 8
The Transmit Direction (TXDIR) control bit selects the direction and source of the clock used to
time the TXSR. If it is not configured as GPIO and when the TXDIR bit is set, the clock is
generated internally and is an output to the SSI_TCK_OUT pin. When cleared, the TXDIR bit
clock source is external. The internal clock generator is disconnected from the SSI_TCK_OUT
pin. An external clock source can drive this pin to clock the TXSR.
12.4.8.9 Synchronous Mode (SYN)—Bit 7
The Synchronous (SYN) mode control bit enables the Synchronous mode of operation. In this
mode, the transmit and receive sections share a common clock pin and frame sync pin. SYN,
along with RXDIR, controls the Gated Clock mode. The SSI is in a Gated mode when both SYN
and RXDIR are set.
12.4.8.10 Transmit Shift Direction (TSHFD)—Bit 6
The Transmit Shift Direction (TSHFD) control bit determines whether the most or least
significant bit is transmitted first for the transmit section. If the TSHFD bit is set, the LSB is
transmitted first. If the TSHFD bit is cleared, the data is transmitted to the MSB first.
Note: The codec device labels the MSB as bit zero, whereas the SSI labels the LSB as bit
zero. Therefore, when using a standard codec, the SSI MSB, or codec bit zero, is
shifted out first and the TSHFD bit should be cleared.
Freescale Semiconductor
TXDIR RFDIR TFDIR
Asynchronous Mode
0 0 0
1 0 1
0 1 0
1 1 1
Synchronous Mode
0 — 0
1 — 1
0 — —
1 — —
Synchronous Serial Interface (SSI), Rev. 3
SRFS STFS
RFS IN TFS IN
RFS IN TFS OUT
RFS OUT TFS IN
RFS OUT TFS OUT
GPIO FS IN
GPIO FS OUT
GPIO GPIO
GPIO GPIO
Register Definitions
Figure
SRCK STCK
RCK IN TCKIN
RCK IN TCK OUT
RCK OUT TCK IN
RCK OUT TCK OUT
GPIO CK IN
GPIO CK OUT
GPIO Gated IN
GPIO Gated OUT
21