Freescale Semiconductor MC9S12ZVM series Manuals

Manuals and User Guides for Freescale Semiconductor MC9S12ZVM series. We have 1 Freescale Semiconductor MC9S12ZVM series manual available for free PDF download: Reference Manual

Freescale Semiconductor MC9S12ZVM series Reference Manual

Freescale Semiconductor MC9S12ZVM series Reference Manual (825 pages)

16-bit microcontroller

Brand: Freescale Semiconductor | Category: Controller | Size: 4 MB

Table of Contents

Device Overview Mc9S12Zvm-Family

3
- Table of Contents
  3
- Introduction
  17
- Features
  18
- Chapter 1 Functional Differences between 1N95G and 0N95G Masksets
  
  20
  - Module Features
    21
    
    Embedded Memory
    22
    
    Clocks, Reset & Power Management Unit (CPMU)
    23
    
    Timer (TIM)
    24
    
    Serial Communication Interface Module (SCI)
    25
    
    Supply Voltage Sensor (BATS)
    26
    
    Current Sense
    27
    
    Block Diagram
    28
  - Device Memory Map
    29
    
    Part ID Assignments
    32
    
    Detailed External Signal Descriptions
    33
    
    Power Supply Pins
    39
    
    Package and Pinouts
    40
  - Internal Signal Mapping
    46
    
    Motor Control Loop Signals
    47
    
    Device Level PMF Connectivity
    48
    
    Modes of Operation
    49
    
    Low Power Modes
    50
  - Security
    51
    
    Operation of the Secured Microcontroller
    52
    
    Reprogramming the Security Bits
    53
    
    Interrupt Vectors
    54
    
    Effects of Reset
    57
    
    CPMU High Temperature Trimming
    58
    
    SCI Baud Rate Detection
    59
1.13.3.2 Control Loop Timing Considerations

62
- BDCM Complementary Mode Operation
  68
- Async_Reload
  72
- BLDC Six-Step Commutation
  72
- Commutation_Event
  72
- Glb_Ldok
  72
- Pmf
  72
- Tim
  72
- Trigger_0
  72
- Commutation_Event
  73
- PMSM Control
  74
- Adc0
  75
- Glb_Ldok
  75
- Ptu
  75
- Reloada
  75
- Trigger_0
  75
- Trigger_1
  75
- Adc1
  76
- Glb_Ldok
  76
- Power Domain Considerations
  78
  - Introduction
    83
  - Features
    84
  - Memory Map and Register Deﬁnition
    89
- Chapter 2
  
  90
  - Register Map
    90
  - PIM Registers 0X0200-0X020F
    94
  - PIM Generic Registers
    101
  - PIM Generic Register Exceptions
    109
  - Functional Description
    110
  - Registers
    111
  - Pin I/O Control
    112
  - Interrupts
    113
  - Pin Interrupts and Key-Wakeup (KWU)
    114
  - Over-Current Interrupt
    115
  - Introduction
    117
- Chapter 5
  
  118
  - Glossary
    118
    
    Modes of Operation
    119
    
    Memory Map and Register Deﬁnition
    120
    
    Functional Description
    125
- Chapter 3
  
  127
  - Illegal Accesses
    127
  - Uncorrectable ECC Faults
    128
  - Introduction
    129
- Chapter 16
  
  130
  - Glossary
    130
    
    Modes of Operation
    131
    
    External Signal Description
    132
4.3.2 Register Descriptions

133
- Register Descriptions
  133
- 0X000017 INT_CFADDR R
  134
- 0X000018 INT_CFDATA0 R
  134
- Address
  134
- Register Name
  134
- Interrupt Request Conﬁguration Data Register
  135
- Interrupt Request Conﬁguration Data Register 3 (INT_CFDATA3)
  136
- Interrupt Request Conﬁguration Data Register 4 (INT_CFDATA4)
  136
- Interrupt Request Conﬁguration Data Register 5 (INT_CFDATA5)
  136
- Functional Description
  138
- Chapter 4
  
  139
  - Priority Decoder
    139
  - Exception Priority
    140
  - Interrupt Nesting
    141
  - Wake up from Stop or Wait Mode
    142
    
    Introduction
    143
    
    Features
    144
    
    Block Diagram
    146
    
    External Signal Description
    147
  - Bit
    148
    
    Register Descriptions
    148
    
    Functional Description
    152
  - Clock Source
    153
  - BDC Access of Internal Resources
    169
  - BDC Serial Interface
    172
  - Serial Interface Hardware Handshake (ACK Pulse) Protocol
    175
  - Hardware Handshake Abort Procedure
    177
  - Hardware Handshake Disabled (ACK Pulse Disabled)
    178
  - Single Stepping
    179
  - Serial Communication Timeout
    180
  - Introduction
    181
  - Overview
    182
    
    Modes of Operation
    183
    
    External Signal Description
    184
    
    Register Descriptions
    187
    
    Functional Description
    208
- Chapter 6
  
  212
  - Events
    212
  - State Sequence Control
    214
  - Trace Buffer Operation
    215
  - Code Proﬁling
    224
  - Breakpoints
    228
    
    Application Information
    229
    
    Breakpoints from Other S12Z Sources
    230
    
    Introduction
    231
    
    Register Descriptions
    233
    
    Functional Description
    237
  - Aligned 2 and 4 Byte Memory Write Access
    238
- Chapter 7
  
  238
  - Memory Read Access
    239
  - ECC Algorithm
    240
    
    Introduction
    243
    
    Features
    244
    
    Modes of Operation
    246
- Chapter 8
  
  249
  - S12CPMU_UHV_V6 Block Diagram
    249
    
    Signal Description
    251
    
    BCTL— Base Control Pin for External PNP
    252
    
    Memory Map and Registers
    253
    
    Register Descriptions
    255
    
    Functional Description
    293
  - Startup from Reset
    295
  - Full Stop Mode Using Oscillator Clock as Source of the Bus Clock
    296
  - External Oscillator
    297
    
    System Clock Conﬁgurations
    298
    
    Resets
    299
  - Description of Reset Operation
    300
  - Computer Operating Properly Watchdog (COP) Reset
    301
  - Power-On Reset (POR)
    302
  - Description of Interrupt Operation
    303
    
    Initialization/Application Information
    305
    
    Introduction
    307
- Chapter 9
  
  309
  - Key Features
    309
    
    Modes of Operation
    310
    
    Block Diagram
    313
  - Signal Description
    314
9.4 Memory Map and Register Deﬁnition

315
- Memory Map and Register Deﬁnition
  315
- Address Name Bit
  316
- Adc_En
  318
  - Adc_Sr
    318
  - Frz_Mod
    318
  - Register Descriptions
    318
- Csl_Bmod Rvl_Bmod Smod_Acc Aut_Rsta
  320
  - Csl_Sel
    321
  - DBECC_ERR Reserved
    321
  - Rvl_Sel
    321
  - Seqa Trig Rsta
    324
  - Eol_Eie
    328
  - Ia_Eie Cmd_Eie
    328
  - SEQAD_IE CONIF_OIE Reserved
    329
  - Eol_Eif
    330
  - Ia_Eif Cmd_Eif
    330
- Ldok_Eif
  330
- Eol_Ie
  333
- Eol_If
  334
  - Functional Description
    350
  - Digital Sub-Block
    351
  - Resets
    364
  - ADC Error and Conversion Flow Control Issue Interrupt
    365
- Use Cases and Application Information
  366
  - List Usage — CSL Double Buffer Mode and RVL Double Buffer Mode
    367
  - List Usage — CSL Double Buffer Mode and RVL Double Buffer Mode
    368
  - Conversion Flow Control Application Information
    370
  - Continuous Conversion
    372
  - Triggered Conversion — Single CSL
    373
  - Fully Timing Controlled Conversion
    374
  - Introduction
    375
  - Block Diagram
    376
  - Memory Map and Register Deﬁnition
    377
  - Functional Description
    381
  - Introduction
    385
  - Block Diagrams
    386
  - IOC3 - IOC0 — Input Capture and Output Compare Channel 3-0
    387
  - Functional Description
    399
  - Prescaler
    400
- Chapter 10
  
  401
- Chapter 11
  
  401
  - Input Capture
    401
  - Resets
    402
  - Introduction
    403
    
    Glossary
    404
- Chapter 18
  
  405
  - Features
    405
    
    External Signal Description
    406
    
    Memory Map and Register Deﬁnition
    407
    
    Register Descriptions
    409
- Chapter 12
  
  428
  - Programmer's Model of Message Storage
    428
    
    Functional Description
    439
    
    Identiﬁer Acceptance Filter
    442
  - Modes of Operation
    448
  - Low-Power Options
    450
  - Reset Initialization
    454
  - Initialization/Application Information
    456
    
    Introduction
    457
    
    Modes of Operation
    458
    
    Block Diagram
    459
    
    PTURE — PTUE Reload Event
    460
    
    Register Descriptions
    462
    
    Functional Description
    478
- Chapter 13
  
  480
  - Memory Based Trigger Event List
    480
  - Reload Mechanism
    481
  - Interrupts and Error Handling
    482
  - Debugging
    483
- Chapter 14
  
  485
  - Introduction
    486
  - Modes of Operation
    487
  - Block Diagram
    488
  - Signal Descriptions
    489
    
    Commutation Event Edge Select Signal — Async_Event_Edge_Sel[1:0]
    490
  - Memory Map and Registers
    491
    
    Register Descriptions
    496
    
    Functional Description
    523
    
    Prescaler
    524
    
    Independent or Complementary Channel Operation
    528
    
    Deadtime Generators
    529
    
    Top/Bottom Correction
    531
    
    Asymmetric PWM Output
    537
    
    Variable Edge Placement PWM Output
    538
    
    Double Switching PWM Output
    539
    
    Output Polarity
    541
    
    PWM Generator Loading
    544
    
    Fault Protection
    549
  - Resets
    551
    
    Interrupts
    552
    
    BLDC 6-Step Commutation
    553
  - Introduction
    557
    
    Features
    558
    
    Modes of Operation
    559
  - External Signal Description
    560
    
    Register Descriptions
    561
  - Functional Description
    574
- Chapter 15
  
  575
  - Infrared Interface Submodule
    575
  - Data Format
    576
  - Baud Rate Generation
    577
  - Transmitter
    578
  - Receiver
    583
  - Single-Wire Operation
    591
  - Loop Operation
    592
  - Modes of Operation
    593
  - Recovery from Wait Mode
    596
  - Introduction
    597
    
    Block Diagram
    598
  - External Signal Description
    599
    
    SS — Slave Select Pin
    600
    
    Register Descriptions
    601
  - Functional Description
    609
    
    Master Mode
    610
    
    Slave Mode
    611
    
    Transmission Formats
    612
    
    SPI Baud Rate Generation
    617
    
    Special Features
    618
    
    Error Conditions
    619
    
    Low Power Mode Options
    620
    
    Introduction
    623
    
    Modes of Operation
    624
    
    Block Diagram
    625
    
    External Signal Description
    626
    
    Memory Map and Register Deﬁnition
    628
    
    Register Descriptions
    629
    
    Functional Description
    647
- Chapter 17
  
  648
  - High-Side FET Pre-Driver
    648
  - Charge Pump
    650
  - Desaturation Error
    651
  - Phase Comparators
    652
  - Current Sense Ampliﬁer and Overcurrent Comparator
    656
  - GDU DC Link Voltage Monitor
    657
  - Boost Converter
    658
  - Interrupts
    659
  - Application Information
    660
    
    Calculation of Bootstrap Capacitor
    661
    
    Introduction
    663
    
    Modes of Operation
    664
    
    Block Diagram
    665
    
    External Signal Description
    666
    
    Memory Map and Register Deﬁnition
    667
    
    Register Descriptions
    668
    
    Functional Description
    675
    
    Modes
    676
    
    Interrupts
    679
    
    Application Information
    682
- Chapter 19
  
  685
  - Introduction
    686
  - Features
    687
  - Block Diagram
    688
  - Memory Map and Registers
    689
  - Register Descriptions
    693
  - Functional Description
    713
  - Internal NVM Resource
    714
  - Allowed Simultaneous P-Flash and EEPROM Operations
    719
  - Flash Command Description
    720
  - Interrupts
    736
  - Wait Mode
    737
  - Unsecuring the MCU Using Backdoor Key Access
    738
  - Mode and Security Effects on Flash Command Availability
    739
  - A.1 General
    741
- Appendix A
  
  741
- Appendix E
  
  773
- Appendix B Appendix E
  
  774
- Appendix E
  
  775
- Appendix E
  
  776
  - F.1 NVM Timing Parameters
    777
  - F.2 NVM Reliability Parameters
    780
- Appendix F
  
  781
- Appendix G
  
  781
  - G.1 Static Electrical Characteristics
    781
  - G.2 Dynamic Electrical Characteristics
    782
- Appendix H
  
  783
  - H.1 Master Mode
    783
- Appendix I
  
  793
- Appendix J
  
  793
- Appendix K
  
  793
- Appendix L
  
  793
  - L.1 0X0000–0X0003 Part ID
    793
  - L.2 0X0010–0X001F S12ZINT
    794
  - L.4 0X0100-0X017F S12ZDBG
    795
  - L.5 0X0200-0X02Ff PIM
    799
  - L.6 0X0380-0X039F FTMRZ128K512
    803
  - L.7 0X03C0-0X03Cf SRAM_ECC_32D7P
    804
  - L.8 0X0500-X053F PMF15B6C
    805
  - L.9 0X0580-0X059F PTU
    809
  - L.10 0X05C0-0X05Ff TIM0
    811
  - L.11 0X0600-0X063F ADC0
    813
  - L.12 0X0640-0X067F ADC1
    815
  - L.13 0X06A0-0X06Bf GDU
    817
  - L.14 0X06C0-0X06Df CPMU
    818
  - L.15 0X06F0-0X06F7 BATS
    820
  - L.17 0X0710-0X0717 SCI1
    822
  - L.19 0X0800–0X083F CAN0
    823
  - L.20 0X0980-0X0987 LINPHY0
    824

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