Freescale Semiconductor MPC5604B Manuals

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Freescale Semiconductor MPC5604B Reference Manual (934 pages)

Microcontroller

Brand: Freescale Semiconductor | Category: Controller | Size: 11.36 MB

Table of Contents
14
Overview
30
Appendix B

33
Revision History

33
- References
  34
Chapter 1 Reference Manual Content

35
- Using the MPC5604B
  36
  - Input/Output Pins
    37
  - Software Design
    38
- The MPC5604B Microcontroller Family
  40
- Block Diagram
  43
Chapter 2 Chip-Level Features

44
- Packages
  45
- Introduction
  50
Chapter 3

53
Chapter 4

53
- Pad Configuration During Reset Phases
  53
- Voltage Supply Pins
  54
- System Pins
  55
- Nexus 2+ Pins
  72
- Boot Mechanism
  74
Chapter 5

75
- Flash Memory Boot
  75
- Serial Boot Mode
  77
- Boot Assist Module (BAM)
  82
  - Linflex (RS232) Boot
    90
  - Flexcan Boot
    91
- System Status and Configuration Module (SSCM)
  93
- Modes of Operation
  94
Chapter 6

104
- Clock Architecture
  104
- Clock Gating
  105
- Fast External Crystal Oscillator (FXOSC) Digital Interface
  106
- Register Description
  107
- Slow External Crystal Oscillator (SXOSC) Digital Interface
  108
- Register Description
  109
- Slow Internal RC Oscillator (SIRC) Digital Interface
  110
- Register Description
  111
- Fast Internal RC Oscillator (FIRC) Digital Interface
  112
  - Register Description
    113
  - Features
    114
  - Register Description
    115
  - Functional Description
    118
  - Recommendations
    121
- Main Features
  122
- Functional Description
  123
- Memory Map and Register Description
  125
- Overview
  130
  - Features
    131
  - Modes of Operation
    132
  - Register Descriptions
    136
  - Functional Description
    140
Chapter 7

141
- Output Clock Multiplexing
  141
- Output Clock Division Selection
  142
  - Introduction
    144
  - Features
    146
  - External Signal Description
    147
  - Register Description
    155
  - Functional Description
    177
Chapter 8

178
- Modes Details
  178
- Mode Transition Process
  183
- Protection of Mode Configuration Registers
  193
- Peripheral Clock Gating
  195
- Application Example
  196
  - Introduction
    198
  - Features
    199
  - Modes of Operation
    200
  - External Signal Description
    201
  - Register Descriptions
    203
  - Functional Description
    214
- Destructive Resets
  218
- Functional Resets
  219
- Boot Mode Capturing
  220
  - Introduction
    222
  - Features
    223
  - External Signal Description
    224
  - Register Descriptions
    225
  - Functional Description
    229
- Initialization Information
  232
Chapter 10 Voltage Regulators

234
Chapter 11 Ultra Low Power Regulator (ULPREG)

235
- Register Description
  236
- Power Domain Organization
  237
  - Overview
    240
  - Features
    242
Chapter 12

243
- NMI Status Flag Register (NSR)
  243
- NMI Configuration Register (NCR)
  244
- Wakeup/Interrupt Status Flag Register (WISR)
  245
- Interrupt Request Enable Register (IRER)
  246
- Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER)
  247
- Wakeup/Interrupt Filter Enable Register (WIFER)
  248
- Functional Description
  249
- External Wakeups/Interrupts
  251
- On-Chip Wakeups
  252
- Overview
  254
Chapter 13 Device-Specific Information

256
- Debug Mode
  257
- RTC Control Register (RTCC)
  258
- RTC Status Register (RTCS)
  260
- RTC Counter Register (RTCCNT)
  261
- API Functional Description
  262
  - Introduction
    264
  - Register Description
    265
  - Functional Description
    267
Chapter 14

268
- Baud Rate Generation
  268
- Overview
  272
Chapter 17

274
- Block Diagram
  274
  - Instruction Unit Features
    275
  - Load/Store Unit Features
    276
- Core Registers and Programmer's Model
  277
  - Introduction
    280
  - Block Diagram
    281
  - Modes of Operation
    282
  - Memory Map and Register Description
    283
  - Register Description
    284
  - Functional Description
    291
Chapter 16

300
- Interrupt Request Sources
  300
- Handshaking with Processor
  302
- Initialization/Application Information
  304
- ISR, RTOS, and Task Hierarchy
  306
- Order of Execution
  307
- Priority Ceiling Protocol
  308
- Software Configurable Interrupt Requests
  309
- Lowering Priority Within an ISR
  310
- Examining LIFO Contents
  311
  - Introduction
    312
  - Overview
    313
- General Operation
  314
- Slave Ports
  315
  - Introduction
    318
  - Features
    319
  - Modes of Operation
    320
  - Register Description
    321
  - Functional Description
    333
Chapter 18 Putting It All Together and AHB Error Terminations

335
- Introduction
  338
- Features
  340
Chapter 19

341
- Detailed Signal Descriptions
  341
- Memory Map and Register Description
  342
  - Register Protection
    343
  - Register Descriptions
    344
  - Functional Description
    361
  - External Interrupts
    362
- Pin Muxing
  363
- Introduction
  366
- Block Diagram
  367
  - Functional Description
    378
  - Interrupts
    382
  - Initialization/Application Information
    383
  - Introduction
    388
- General Description
  389
- Fractional Baud Rate Generation
  390
  - Operating Modes
    392
  - Initialization Mode
    393
  - Self Test Mode
    394
  - Functional Description
    420
Chapter 21 LIN Mode

422
- Bit Timeout Counter
  430
- Interrupts
  432
- Introduction
  434
- Flexcan Module Features
  435
- Modes of Operation
  436
- Signal Descriptions
  437
- Message Buffer Structure
  439
  - Rx FIFO Structure
    442
  - Register Description
    444
  - Functional Description
    462
- Local Priority Transmission
  463
- Arbitration Process
  464
- Receive Process
  465
- Matching Process
  466
- Data Coherence
  467
- Rx FIFO
  470
- CAN Protocol Related Features
  471
  - Modes of Operation Details
    475
  - Interrupts
    476
  - Initialization/Application Information
    477
- Flexcan Addressing and SRAM Size Configurations
  478
  - Introduction
    480
  - Features
    481
  - Modes of Operation
    482
Chapter 23

483
- Debug Mode
  483
- Memory Map and Register Description
  485
- DSPI Module Configuration Register (Dspix_Mcr)
  486
- DSPI Transfer Count Register (Dspix_Tcr)
  489
- DSPI Status Register (Dspix_Sr)
  497
- DSPI Interrupt Request Enable Register (Dspix_Rser)
  499
- DSPI PUSH TX FIFO Register (Dspix_Pushr)
  501
- DSPI POP RX FIFO Register (Dspix_Popr)
  503
- DSPI Transmit FIFO Registers 0–3 (Dspix_Txfrn)
  504
- Functional Description
  505
- Modes of Operation
  506
  - Start and Stop of DSPI Transfers
    507
  - Serial Peripheral Interface (SPI) Configuration
    508
  - DSPI Baud Rate and Clock Delay Generation
    511
  - Transfer Formats
    514
  - Continuous Serial Communications Clock
    522
  - Interrupt Requests
    525
  - Power Saving Features
    526
- Initialization and Application Information
  527
  - Delay Settings
    529
Chapter 24 Timers

532
- Introduction
  534
- Overview of the STM
  536
- Overview of the PIT
  538
- External Signal Description
  539
- Functional Description
  543
- External Signal Description
  546
- Functional Description
  558
- Initialization/Application Information
  588
- Periodic Interrupt Timer (PIT)
  591
- Features
  592
  - Functional Description
    597
  - Initialization and Application Information
    598
- Overview
  602
Chapter 25

603
- Device-Specific Implementation
  603
- Functional Description
  604
- Analog Clock Generator and Conversion Timings
  608
- ADC CTU (Cross Triggering Unit)
  610
- Presampling
  611
- Programmable Analog Watchdog
  612
- Interrupts
  613
- External Decode Signals Delay
  614
- Register Descriptions
  615
- Control Logic Registers
  618
- Interrupt Registers
  622
- Threshold Registers
  629
- Presampling Registers
  630
- Mask Registers
  633
- Delay Registers
  638
- Data Registers
  639
- Introduction
  642
- Functional Description
  644
Chapter 26 Channel Value

646
Chapter 32

650
- Introduction
  650
- Main Features
  651
- Functional Description
  652
  - Flash Memory Module Sectorization
    653
  - Testflash Block
    654
  - Shadow Sector
    656
- Reset
  657
  - Power-Down Mode
    658
  - Register Description
    659
  - Cflash Register Description
    660
  - Dflash Register Description
    691
- Programming Considerations
  714
  - Double Word Program
    715
  - Sector Erase
    717
- Platform Flash Memory Controller
  725
- Memory Map and Register Description
  728
- Functional Description
  737
  - Access Protections
    738
  - Access Pipelining
    739
  - Bank1 Temporary Holding Register
    741
  - Read-While-Write Functionality
    742
  - Wait-State Emulation
    743
- Introduction
  746
Chapter 28

747
- Access Timing
  747
- Reset Effects on SRAM Accesses
  748
- Introduction
  752
- Modes of Operation
  753
  - Memory Map
    754
Chapter 31

755
- Register Description
  755
- Functional Description
  757
  - Access Errors
    761
Chapter 30

766
- Overview
  766
- External Signal Description
  767
  - Register Description
    768
  - Functional Description
    772
Chapter 27

774
- Introduction
  774
  - Register Description
    775
  - Register Protection
    794
Chapter 29

798
- Introduction
  798
- Features
  799
- External Signal Description
  800
- Memory Map and Register Description
  801
  - Boundary Scan Register
    802
  - TAP Controller State Machine
    803
  - JTAGC Instructions
    805
  - Boundary Scan
    807
  - E200Z0 Once Controller Functional Description
    808
    
    Initialization/Application Information
    810
    
    Introduction
    812
- Features
  813
- Modes of Operation
  814
Chapter 33 Operating Mode

815
- Nexus Debug Interface Registers
  816
- Register Description
  817
- Functional Description
  826
- Enabling Nexus Clients for TAP Access
  827
- Configuring the NDI for Nexus Messaging
  828
- Debug Mode Control
  829
Appendix A

832
- Register Map
  833
- Register Map
  834
- Register Map
  835
- Register Map
  836
- Register Map
  837
- Register Map
  838
- Register Map
  839
- Register Map
  840
- Register Map
  841
- Register Map
  842
- Register Map
  843
- Register Map
  844
- Register Map
  845
- Register Map
  846
- Register Map
  847
- Register Map
  848
- Register Map
  849
- Register Map
  850
- Register Map
  851
- Register Map
  852
- Register Map
  853
- Register Map
  854
- Register Map
  855
- Register Map
  856
- Register Map
  857
- Register Map
  858
- Register Map
  859
- Register Map
  860
- Register Map
  861
- Register Map
  862
- Register Map
  863
- Register Map
  864
- Register Map
  865
- Register Map
  866
- Register Map
  867
- Register Map
  868
- Register Map
  869
- Register Map
  870
- Register Map
  871
- Register Map
  872
- Register Map
  873
- Register Map
  874
- Register Map
  875
- Register Map
  876
- Register Map
  877
- Register Map
  878
- Register Map
  879
- Register Map
  880
- Register Map
  881
- Register Map
  882
- Register Map
  883
- Register Map
  884
- Register Map
  885
Register Map

886
- Register Map
  887
- Register Map
  888
- Register Map
  889
- Register Map
  890
- Register Map
  891
- Register Map
  892
- Register Map
  893
- Register Map
  894
- Register Map
  895
- Register Map
  896
- Register Map
  897
- Register Map
  898
- Register Map
  899
- Register Map
  900
- Register Map
  901
- Register Map
  902
- Register Map
  903
- Register Map
  904
- Register Map
  905
- Register Map
  906
- Register Map
  907
- Register Map
  908
- Register Map
  909
- Register Map
  910
- Register Map
  911
- Register Map
  912
- B.1 Changes between Revisions 7 and 8
  914
- B.2 Changes between Revisions 5 and 7
  919
- B.3 Changes between Revisions 4 and 5
  921
- B.4 Changes between Revisions 2 and 4
  922
- B.5 Changes between Revisions 1 and 2
  931

Freescale Semiconductor MPC5604B Quick Start Manual (150 pages)

based on Qorrivva architecture

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 11.36 MB

Table of Contents
2
Introduction
7
Chapter 1 

10
- ME: Mode Entry Modules
  10
  - Introduction
    10
  - Enabling Modes
    11
  - Configuring Modes
    11
  - Configuring Peripherals
    12
  - Device Mode Selection
    13
- CGM: Clock Generation Module
  14
  - Clock Architecture
    14
  - Clock out
    15
  - Sysclk
    16
  - Fmpll
    17
- A Device Initialisation Procedure
  19
- SWT: Software Watchdog Timer
  20
Chapter 2 SIUL: System Integration Unit Line

21
- Introduction
  21
- Pad Configuration
  21
- GPIO: General Purpose Input/Output
  23
- External Interrupts
  25
Chapter 3 INTC: Interrupt Controller

27
- Introduction
  27
- INTC Configuration (Software Mode)
  29
- Hardware Mode INTC
  30
Chapter 4 Timer Modules

32
Chapter 5 Emios: Enhanced Modular I/O Subsystem

38
Chapter 6 ADC: Analog-To-Digital Converter

54
- Presentation of the ADC Module
  54
  - Introduction
    54
  - Conversion
    55
  - ADC Clock and Conversion Timing
    56
  - Pre-Sampling
    57
  - Analog Watchdog
    57
  - Low Power Consumption Modes
    57
- ADC Configuration
  58
  - Pad Configuration
    58
  - General Registers
    58
  - Conversion Registers
    59
  - Interrupt Registers
    60
  - Watchdog Registers
    60
  - Channel Registers
    61
- ADC Example with PIT and Emios
  61
Chapter 7 CTU: Cross Triggering Unit

64
- Introduction
  64
- Configuring CTU
  65
- Configuring ADC
  66
- Implementing a Feedback Loop with ADC-CTU-Emios
  66
Chapter 8 WKPU: Wakeup Unit

68
- Low Power Consumption Modes
  68
  - Stop
    68
  - Standby
    68
- Introduction
  69
- Configuration of Wakeup Events
  71
Chapter 9 DSPI: Deserial Serial Peripheral Interface

72
- Introduction
  72
  - SPI Protocol Description
    72
  - Module Presentation
    74
- Configuration
  75
  - Signal Configuration
    75
  - Module Configuration Register
    75
  - Transfer Configuration Register
    76
  - Data Attributes
    77
  - Baud Rate
    78
  - CS to SCK Delay
    79
  - After SCK Delay
    79
  - After Transfer Delay
    79
  - Status and Interrupt Registers
    79
  - Transmit/Receive Registers
    80
- Developing a General Purpose SPI Driver
  81
- Driving Smart-MOS Switches MC33984 Using SPI Driver
  83
  - Introduction to MC33984
    83
  - Driver's Components
    83
  - Definitions
    85
  - Initialization
    85
  - Operations
    86
  - User Interface
    86
  - Testing
    86
Chapter 10 UART: Universal Asynchronous Receiver Transmitter

88
- Introduction to UART
  88
- Module Presentation
  88
- Configuration
  89
- Developing a General Purpose UART Driver
  93
- Using the UART Driver for a Terminal Interface
  94
  - System Initialisation
    94
  - SIUL Configuration
    94
  - ADC Configuration
    95
  - Emios Configuration
    96
  - Main Procedure and Use of the Driver
    96
  - Results
    98
Chapter 11 I²C: Inter-Integrated Circuit Bus Controller

100
- Presentation of I²C Protocol
  100
  - Description
    100
  - Baud Rate
    101
  - Pull-Up Resistor Calculation
    102
- Using the I²C Module
  102
  - Module Presentation
    102
  - Module Registers
    103
  - Communication
    105
  - Developing a General Purpose I²C Driver
    107
Chapter 12 CAN: Controller Area Network

108
- CAN Protocol
  108
  - Introduction
    108
  - Frame Description
    109
  - Physical Layer
    110
  - Error Detection
    111
  - Bit-Rate and Sampling
    112
- Flexcan Module Configuration
  113
  - Module Description
    113
  - Message Buffer Mode and RX FIFO Mode
    114
  - Message Buffers
    114
  - RX FIFO Engine
    116
  - Configuration Registers
    117
  - Status and Interrupt Registers
    119
- Flexcan Usage Explained with an Example
  121
  - Initialisation
    122
  - Transmission
    122
  - Reception
    123
  - Interrupt Handling
    123
- CAN Transceiver(MCZ33905S5EK) Configuration
  124
Appendix 1 Using Code Warrior IDE

126
Appendix 2 Pad Configurations

133
Appendix 3 Peripheral Input Pin Selection

141
Appendix 4 Interrupt Vector Table

143
Appendix 5 I²C Baud Rate Prescaler Values

148

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Freescale Semiconductor MPC5604B Manuals

Freescale Semiconductor MPC5604B Reference Manual (934 pages)

Table of Contents

Appendix B

Revision History

Chapter 1 Reference Manual Content

Chapter 2 Chip-Level Features

Chapter 3

Chapter 4

Chapter 5

Chapter 6

Chapter 7

Chapter 8

Chapter 10 Voltage Regulators

Chapter 11 Ultra Low Power Regulator (ULPREG)

Chapter 12

Chapter 13 Device-Specific Information

Chapter 14

Chapter 17

Chapter 16

Chapter 18 Putting It All Together and AHB Error Terminations

Chapter 19

Chapter 21 LIN Mode

Chapter 23

Chapter 24 Timers

Chapter 25

Chapter 26 Channel Value

Chapter 32

Chapter 28

Chapter 31

Chapter 30

Chapter 27

Chapter 29

Chapter 33 Operating Mode

Appendix A

Register Map

Freescale Semiconductor MPC5604B Quick Start Manual (150 pages)

Table of Contents

Chapter 1 

Chapter 2 SIUL: System Integration Unit Line

Chapter 3 INTC: Interrupt Controller

Chapter 4 Timer Modules

Chapter 5 Emios: Enhanced Modular I/O Subsystem

Chapter 6 ADC: Analog-To-Digital Converter

Chapter 7 CTU: Cross Triggering Unit

Chapter 8 WKPU: Wakeup Unit

Chapter 9 DSPI: Deserial Serial Peripheral Interface

Chapter 10 UART: Universal Asynchronous Receiver Transmitter

Chapter 11 I²C: Inter-Integrated Circuit Bus Controller

Chapter 12 CAN: Controller Area Network

Appendix 1 Using Code Warrior IDE

Appendix 2 Pad Configurations

Appendix 3 Peripheral Input Pin Selection

Appendix 4 Interrupt Vector Table

Appendix 5 I²C Baud Rate Prescaler Values

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