Table of Contents
Advertisement
Application:
COP
arch.h: ArchIO.Cop.ControlReg
registers.h: ArchIO_Cop_ControlReg
Stop Enable
COP counter stops in Stop mode
COP counter runs in Stop mode
Note:
This bit can only be changed when the CWP
bit is set to zero. For the COP to run in Stop
mode, the CEN bit must also be set.
COP Wait Enable
COP counter will Stop in Wait mode
COP counter will run in Wait mode
Note:
This bit can only be changed when the CWP
bit is set to zero. For the COP to run in Stop
mode, the CEN bit must also be set.
Bits
Control Register
Read
(COPCTL)
Write
SYS_BASE+$0
Reset
Reserved Bits
Freescale Semiconductor
COP Control Register (COPCTL)
CSEN
0
1
CWEN
0
1
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
Appendix B - Programmer's Sheets, Rev. 3
Date:
Programmer:
CEN
0
COP is disabled
1
COP is enabled
Note: This bit can only be changed when CWP is set
to zero. Once this bit has been written to a 1, it
cannot be changed back to 0 without resetting
the COP module.
CWP
COP Write Protect
COPCTL, COPTO registers are readable
0
and writeable
COPCTL, COPTO registers are
1
read-only
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
0
1 of 3
Sheet
COP Enable
3
2
1
0
CSEN CWEN CEN CWP
0
0
0
0
113
Advertisement
Table of Contents
Need help?
Do you have a question about the 56F800 and is the answer not in the manual?