Functional Description; Counting Options; External Inputs; Oflag Output Signal - Freescale Semiconductor 56F800 User Manual

Functional Description

Each timer/counter in the 56F827 has following additional registers:
• Quad Timer Comparator Load (CMPLD1 and CMPLD2) registers
• Quad Timer Comparator Status and Load Registers (COMSCR)
For information about TMRA registers please refer to
12.5 Functional Description
The counter/timer has two basic modes of operation:
1. Count internal or external events.
2. Count an internal clock source while an external input signal is asserted, thus timing the
width of the external input signal.

12.5.1 Counting Options

The counter can count the rising, falling, or both edges of a selected input pin. The counter can
decode and count quadrature encoded input signals. The counter can count up and down using
dual inputs in a count with direction format. The counter's terminal count value, modulus, may
be programmed. The value loaded into the counter after reaching its terminal count may also be
programmed. The counter can count repeatedly, or it can stop after completing one count cycle.
The counter can be programmed to count to a programmed value and then immediately
reinitialize, or it can count through the compare value until the count moves to zero.

12.5.2 External Inputs

The external inputs to each counter/timer can be shared among each of the four counter/timers
within a module. The external inputs can be used as count commands and timer commands. They
can trigger the current counter value to be captured and then be used to generate interrupt
requests. The polarity of the external inputs are selectable.

12.5.3 OFLAG Output Signal

The primary output of each counter/timer is the output signal, OFLAG. The OFLAG output
signal can be set, cleared, or toggled when the counter reaches the programmed value. The
OFLAG output signal may be output to an external pin shared with an external input signal. The
OFLAG output signal enables each counter to generate square waves, PWM, or pulse stream
outputs. The polarity of the OFLAG output signal is selectable.
6
Table
56F826/827 User Manual, Rev. 3
3-11.
Freescale Semiconductor