Address Generation Unit (Agu); Program Controller And Hardware Looping Unit - Freescale Semiconductor 56F800 User Manual

The Data ALU is capable of performing the following in one instruction cycle:
• Multiplication
• Multiply-accumulate with positive or negative accumulation
• Addition
• Subtraction
• Shifting
• Logical operations
Arithmetic operations are completed using two's-complement fractional or integer arithmetic.
Support is also provided for unsigned and multi-precision arithmetic.
Data ALU source operands can be 16, 32, or 36 bits and can originate from input registers and/or
accumulators. ALU results are stored in one of the accumulators. Additionally, some arithmetic
instructions store their 16-bit results in any of the three Data ALU input registers, or write
directly to memory. Arithmetic operations and shifts have a 16-bit or 36-bit result, and logical
operations are performed on 16-bit operands yielding 16-bit results. Data ALU registers can be
read or written by the Core Global Data Bus (CGDB) as 16-bit operands, and the X0 register can
also be written by the X Data Bus two (XDB2) with a 16-bit operand.

1.7.2 Address Generation Unit (AGU)

The Address Generation Unit (AGU) performs all of the effective address calculations and
address storage necessary to address data operands in memory. This unit operates in parallel with
other chip resources to minimize address generation overhead. It contains two ALUs, allowing
the generation of up to two 16-bit addresses every instruction cycle—one for either the XAB1 or
Program Address Bus (PAB) and one for the XAB2 bus. The ALU can directly address 65,536
locations on the XAB1 or XAB2 bus. The ALU can also directly address 65,536 locations on the
PAB, for a total capability of 131,072 16-bit data words. Hooks are provided on the 56800 core
allowing expansion of address space. Its arithmetic unit can perform linear and modulo
arithmetic.

1.7.3 Program Controller and Hardware Looping Unit

The Program Controller performs:
• Instruction prefetch
• Instruction decoding
• Hardware loop control
• Interrupt (exception) processing
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