Features; Pin Descriptions; Register Summary - Freescale Semiconductor 56F800 User Manual

12.2 Features

• Each timer module consists of four, 16-bit counters/timers
• Count up/down
• Counters may be cascaded
• Programmable count modulo
• Maximum count rate equals peripheral clock rate/2 when counting external events
• Maximum count rate equals peripheral clock rate when using internal clocks
• Count once or repeatedly
• Counters are preloadable
• Compare registers are preloadable only on the 56F827
• Counters can share available input pins
• Each counter has a separate prescaler
• Each counter has capture and compare capability

12.3 Pin Descriptions

Pins available for the 56F826 and 56F827 are different. Please pay special attention to the
available pins discussed in

12.4 Register Summary

A suffix is added to each register reflecting Quad Timer module A and channel, or group, being
accessed: TMRA0, TMRA1, TMRA2, TMRA3.
For example, the CNTR register for Quad Timer A, channel zero TMRA0 module is called
TMRA0_CNTR.
Each timer/counter in the 56F80x has the following registers:
• Quad Timer Counter (CNTR) register
• Quad Timer Load (LOAD) register
• Quad Timer Hold (HOLD) register
• Quad Timer Capture (CAP) register
• Quad Timer Compare (CMP1 and CMP2) registers
• Quad Timer Status and Control Register (SCR)
• Quad Timer Control (CTRL) register
Freescale Semiconductor
Section 12.8.
Quad Timer Module (TMR), Rev. 3
Register Summary
5