Freescale Semiconductor 56F800 User Manual page 257

For a 9-bit (all 0s or 1s) data character, data sampling of the STOP bit takes the receiver:
10-bit × 16 RT cycles + 10 RT cycles = 170 RT cycles
With the misaligned character, illustrated in
the point when the count of the transmitting device is:
The maximum percentage difference between the receiver count and the transmitter count of a
fast 9-bit character with no errors is:
10.4.4.6 Receiver Wake-Up
In order for the SCI to ignore transmissions intended only for other receivers in multiple receiver
systems, the receiver can be put into a standby state. Setting the Receiver Wake-Up (RWU) bit in
the SCICR puts the receiver into a standby state while receiver interrupts are disabled.
The transmitting device can address messages to selected receivers by including addressing
information in the initial frame or frames of each message.
The WAKE bit in the SCICR determines how the SCI is brought out of the standby state to
process an incoming message. The WAKE bit enables either Idle Input Line Wake-Up or
Address Mark Wake-Up:
• Idle Input Line Wake-Up (WAKE = 0)—In this wake-up method, an idle condition on the
RXD pin clears the RWU bit, waking up the SCI. Idle Input Line Wake-Up requires
messages be separated by at least one preamble, and no message contains preambles. The
initial frame or frames of every message contains addressing information. All receivers
evaluate the addressing information. Receivers of the message then process the following
frames. Any receiver a message does not address can set its RWU bit, returning to the
standby state. The RWU bit remains set and the receiver remains on standby until another
preamble appears on the RXD pin.
The receiver-waking preamble does not set the Receiver Idle (RIDLE) bit or the Receive
Data Full Register (RDRF) flag.
With the WAKE bit clear, setting the RWU bit after the RXD pin has been idle can cause
the receiver to wake-up immediately.
• Address Mark Wake-Up (WAKE = 1)—In this wake-up method, a Logic 1 in the MSB
position of a frame clears the RWU bit, awakening the SCI. The Logic 1 in the MSB position
marks a frame as an address frame containing addressing information. The address frame
Freescale Semiconductor
Figure
11-bit × 16 RT cycles = 176 RT cycles
170 -176
×
100
---------------------
170
Serial Communications Interface (SCI), Rev. 3
10-7, the receiver counts 170 RT cycles at
= 3.53%
Functional Description
15