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Freescale Semiconductor FlexRay MFR4310 Reference Manual

Communication controllers
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MFR4310
Reference Manual
FlexRay
Communication
Controllers
MFR4310RM
Rev. 2
03/2008
freescale.com

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Summary of Contents for Freescale Semiconductor FlexRay MFR4310

  • Page 1 MFR4310 Reference Manual FlexRay Communication Controllers MFR4310RM Rev. 2 03/2008 freescale.com...
  • Page 3 MFR4310 Reference Manual MFR4310RM Rev. 2 03/2008...
  • Page 4 Updated Table A-1 (maximum junction temperature changed from +150C to +140C). Updated Table A-5. Thermal Characteristics Updated Table A-8. Supply Current Characteristics (50mA max for -40 C, 25C & 140 C). Updated Table A-12. Oscillator Characteristics (VDCbias TYP = 2.5). MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 5 Device Overview FlexRay Module (FLEXRAYV4) Port Integration Module (PIM) Dual Output Voltage Regulator (VREG3V3V2) Clocks and Reset Generator (CRG) Oscillator (OSCV2) Electrical Characteristics Package Information Printed Circuit Board Layout Recommendations Index of Registers MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 6 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 7: Table Of Contents

    3.1.3 Color Coding ............60 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 8 4.1.1 Overview ............207 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 9 Functional Description ............226 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 10 A.6 HCS12 Interface Timing ............255 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 11 B.1 64-pin LQFP package ............257 Appendix C Printed Circuit Board Layout Recommendations Appendix D Index of Registers MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 12 Section Number Title Page MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 13 Macrotick Counter Register (MTCTR) ........96 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 14 Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR) ... 118 Figure 3-56. Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR) ... 118 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 15 ....... . . 129 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 16 Figure 3-126. Inconsistent Channel Assignment......... . 178 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 17 Clock Monitor Failure ..........231 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 18 64-pin LQFP Mechanical Dimensions (Case N 840F-02) (Page 3) ....259 Figure C-1. Recommended PCB Layout (64-pin LQFP) for Standard Pierce Oscillator Mode ..262 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 19 Table 3-20. PIER1 Field Descriptions ..........85 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 20 Table 3-55. SSCR0–SSCR3 Field Descriptions......... . 113 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 21 Table 3-89. Individual Message Buffer Types ......... . . 152 Table 3-90. Single Transmit Message Buffer Access Regions Description..... 153 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 22 MFR4310 Relevant Pins for the CRG........224 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 23 Suggested External Component Values ........261 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 24 Table Number Title Page MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 25: Audience

    Communication Controller Module. Audience This reference manual is intended for application and system hardware developers who wish to develop products for the FlexRay MFR4310. It is assumed that the reader understands FlexRay protocol functionality and microcontroller system design. Additional Reading For additional reading that provides background to, or supplements, the information in this manual: •...

  • Page 26: Terminology

    Microtick. A microtick is one CLK_CC period long, and starts on the rising edge of CLK_CC. Macrotick Media Access Test Symbol Network Idle Time Protocol Engine Physical Layer Interface Physical Layer Protocol Operation Control Sequencer Engine Reception Time Control Unit Transmission MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 27: Part Number Coding

    C to +125 Maskset Identifier First character usually identifies wafer fab Suffix Second character usually identifies mask revision Device Title Controller Family Qualification S = Maskset specific part number Figure 1-1. Order Part Number Coding MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 28 Introduction MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 29: Device Overview

    — Double buffered transmit message buffer (combines two single buffered message buffer) • Individual message buffer reconfiguration supported — Means provided to safely disable individual message buffers — Disabled message buffers can be reconfigured MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 30 Hardware selectable clock output to drive external host devices: disabled, 4, 10, or 40 MHz • Maskable interrupt sources available over one interrupt output line • RESET# glitch filter • Electrical physical layer interface compatible with dedicated FlexRay physical layer • Four multiplexed debug strobe pins MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 31: Block Diagram

    D15/PB0 BSEL0#/DBG1 Bus Interface BSEL1#/DBG0 Receiver A Receiver B RXD_BG1 RXD_BG2 TXD_BG2/IF_SEL0 TXD_BG1/IF_SEL1 Transmitter A Transmitter B TXEN2# TXEN1# DBG3/CLK_S1 Debug DBG2/CLK_S0 FlexRay Module VDDX[1:4] TEST VSSX[1:4] Figure 2-1. MFR4310 Functional Block Diagram MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 32: Memory Map

    For detailed information on the MFR4310 CRG module registers, see Chapter 6, “Clocks and Reset Generator (CRG)”. For detailed information on the MFR4310 PIM module registers, see Chapter 4, “Port Integration Module (PIM)”. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 33: Part Id And Module Version Number Assignments

    Section 2.4.2, “Pin Functions and Signal Properties”. Figure 2-2 shows the pin assignments. NOTE For a recommended printed circuit board layout, see Appendix C, “Printed Circuit Board Layout Recommendations”. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 34: Figure 2-2. Mfr4310 Pin Assignment

    D10/PB5 DBG3/CLK_S1 D11/PB4 TXD_BG2/IF_SEL0 D12/PB3 TXEN2# D13/PB2 RXD_BG2 D14/PB1 DBG2/CLK_S0 VDDX1 TXD_BG1/IF_SEL1 VSSX1 D1/PA6 D15/PB0 D0/PA7 A1/XADDR19 VSSX2 A2/XADDR18 VDDX2 A3/XADDR17 TXEN1# A4/XADDR16 VDDX4 A5/XADDR15 A12/ACS2 RESET# RXD_BG1 Figure 2-2. MFR4310 Pin Assignment MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 35: Pin Functions And Signal Properties

    D15 is the MSB of the AMI/MPC data bus; PB0 is the LSB of the HCS12 address/data bus VDDX I/O Z/DC/PC AMI/MPC data bus; HCS12 multiplexed address/data bus VDDX I/O Z/DC/PC AMI/MPC data bus; HCS12 multiplexed address/data bus MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 36 52 A10 ECLK_CC VDDX AMI/MPC address bus; HCS12 clock input Physical Layer Interface 33 RXD_BG1 VDDX PHY Data receiver input 43 RXD_BG2 VDDX PHY Data receiver input 36 TXEN1# VDDX Transmit enable for PHY MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 37 Supply voltage, supply to pin drivers and internal Voltage Regulator 19 VSSR Supply voltage ground, ground to pin drivers and internal Voltage Regulator 50 VDDA Supply analog voltage 49 VSSA Supply analog voltage ground MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 38: Detailed Signal Descriptions

    A[6:1] are AMI/MPC interface address signals. A1 is the LSB of the AMI/MPC address bus. XADDR[14:19] are HCS12 interface expanded address lines. XADDR14 is the LSB of the HCS12 interface expanded address lines. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 39 Section 2.7, “External Host Interface” for more information. These pins can be configured to provide high or reduced output drive, and also to enable or disable pullup or pulldown resistors on the pins. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 40 ECLK_CC is the HCS12 interface clock input signal. (The maximum frequency of this signal can be calculated from the ECLK_CC pulse width low and high times, t and t given in Table A-15.) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 41 Values”. 2.4.3.14 CHICLK_CC — External CHI Clock Input CHICLK_CC is the selectable external CHI clock input. It can be selected to drive the Asynchronous Memory Interface (see Section 2.6.2, “External Host Interface Selection”). MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 42 DBG[3:2] are debug strobe point output signals. The functions output on these pins are selected by the debug port control register. Refer to Section 3.4.16, “Strobe Signal Support” for more information. NOTE CLK_S[1:0] signals are inputs during the internal reset sequence and are latched during the internal reset sequence. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 43: Figure 2-3. Oscillator Connections

    VSSOSC Figure 2-3. Oscillator Connections MFR4310 EXTAL CLKOUT Where: G = 40 MHz CMOS-compatible External Oscillator Not connected XTAL (VDDOSC-Level) (left open) VDDOSC VSSOSC VSSOSC Figure 2-4. External Square Wave Clock Generator Connection MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 44: Power Supply Pins

    External power and ground for I/O drivers and input to the internal voltage regulator. NOTE The VDDR pin enables the internal 3.3 V to 2.5 V voltage regulator. If this pin is tied to ground, the internal voltage regulator is turned off. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 45: Modes Of Operation

    The output frequency of the CLKOUT signal is selected by the CLK_S[1:0] input pins, in accordance with Table 2-5: Table 2-5. CLKOUT Frequency Selection CLKOUT Function CLK_S0 CLK_S1 4 MHz output 10 MHz output MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 46: External Host Interface Selection

    NOTE The following steps must be taken to select a correct external host interface mode. 1. Set IF_SEL0, IF_SEL1 for MPC mode, HCS12 synchronous mode or AMI mode. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 47: Recommended Pullup/Pulldown Resistor Values

    WE# are used to determine the type of access as shown in Table 2-8. Table 2-8. AMI Access Types BSEL1# BSEL0# Type of Access Illegal 16-bit write to word address 8-bit write to even byte address MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 48 For the AMI, D0 is the LSB of the 16-bit data bus. NOTE If the AMI mode without the CHICLK_CC signal is selected (i.e. IF_SEL[1:0] = 0b01), CHICLK_CC must be driven to logic 0 or logic 1 (it must not be left floating). MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 49: Figure 2-5. Ami Interface With S12X Family

    Device Overview 2.7.1.1 Asynchronous Memory Interface with S12X Family S12X Family MFR4310 … … … … BSEL1# BSEL0# VDDXn IRQn INT_CC# TXD_BG2/IF_SEL0 PL Interface TXD_BG1/IF_SEL1 VSSXn Figure 2-5. AMI Interface with S12X Family MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 50: Mpc Interface

    The MPC interface decodes its internal register addresses with help of the chip select signal CE# and the address lines A[12:1]. • The MPC interface accepts only aligned 16-bit read and 8- or 16-bit write transactions. The MPC interface does not support 8-bit read accesses. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 51: Table 2-9. Mpc Interface Access Types

    BSEL[1:0]# inputs indicate the direction of the data transfer for a transaction. • OE# input enables the MPC data output during read transactions. NOTE D0 is the LSB of the 16-bit data bus. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 52: Hcs12 Interface

    ACS[0:2]; PA5 is compared with ACS0, PA6 with ACS1, PA7 with ACS2. NOTE The address decoding phase of a read/write operation is passed if all the comparisons described above are passed. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 53: Table 2-10. Hcs12 Access Types

    RW_CC# indicates the direction of data transfer for a transaction. • INT_CC# is an interrupt line that can be used for requesting, by means of the internal interrupt controller, a service routine from the HCS12 device. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 54: Figure 2-8. Hcs12 Interface Address Decoding And Internal Chip Select Generation

    & ACS[0:2] 3 bit Address XADDR[14:19] Comparator 2 XADDR[14:19] 6 bit 000000 6 bit ADR[14:15] 2 bit 2 bit Address Comparator 3 Figure 2-8. HCS12 Interface Address Decoding and Internal Chip Select Generation MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 55: Figure 2-9. Hcs12 Interface With Hcs12 Page Mode Support

    ADDR/DATA0 (PB0) XADDR19 XADDR19 … … XADDR14 XADDR14 ECLK ECLK_CC LSTRB LSTRB R/W# RW_CC# VDDXn ACS2 ACS1 ACS0 IRQn# INT_CC# TXD_BG1/IF_SEL1 PL Interface TXD_BG2/IF_SEL0 VSSXn Figure 2-9. HCS12 interface with HCS12 Page Mode Support MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 56: Resets And Interrupts

    2.7.3.3 HCS12 Interface Timing Section A.6, “HCS12 Interface Timing” for timing characteristics of the HCS12 interface. Resets and Interrupts 2.8.1 Resets MFR4310 has the following resets: • External hard reset input signal RESET#. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 57: Interrupt Sources

    INT_CC#. Refer to Section 3.4.19, “Interrupt Support” and Section 6.3.2, “Clock and Reset Status Register (CRSR)” for more information on available interrupt sources. The type of interrupt is level sensitive. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 58 Device Overview MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 59: Flexray Module (Flexrayv4)

    For example, Message Buffer Number 5 corresponds to the MBCCS5 register. Microcontroller Unit μT Microtick. A microtick is one CLK_CC period long, and starts on the rising edge of CLK_CC. Macrotick Media Access Test Symbol MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 60: Color Coding

    The FlexRay module has three main components: • Controller host interface (CHI) • Protocol engine (PE) • Clock domain crossing unit (CDC) A block diagram of the FlexRay module with its surrounding modules is given in Figure 3-1. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 61: Features

    FRM for application processing. NOTE The FlexRay module does not provide a memory protection scheme for the FlexRay Memory. 3.1.5 Features The FlexRay module provides the following features: MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 62 — global channel ID filtering — global message ID filtering for the dynamic segment • 4 configurable slot error counters • 4 dedicated slot status indicators — used to observe slots without using receive message buffers MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 63: Modes Of Operation

    The application can transition the protocol engine into other protocol states using the Protocol Operation Control Register (POCR). For details regarding protocol states, see FlexRay Communications System Protocol Specification, Version 2.1 Rev A. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 64: External Signal Description

    The TXD_BG1 signal carries the transmit data for channel A to the corresponding FlexRay bus driver. 3.2.1.4 TXEN1# — Transmit Enable Channel A The TXEN1# signal indicates to the FlexRay bus driver that the FlexRay module is attempting to transmit data on channel A. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 65: Memory Map And Register Description

    Protocol Operation Control Register (POCR) 0x0016 Global Interrupt Flag and Enable Register (GIFER) 0x0018 Protocol Interrupt Flag Register 0 (PIFR0) 0x001A Protocol Interrupt Flag Register 1 (PIFR1) 0x001C Protocol Interrupt Enable Register 0 (PIER0) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 66 Timer Configuration and Control Register (TICCR) 0x005C Timer 1 Cycle Set Register (TI1CYSR) 0x005E Timer 1 Macrotick Offset Register (TI1MTOR) 0x0060 Timer 2 Configuration Register 0 (TI2CR0) 0x0062 Timer 2 Configuration Register 1 (TI2CR1) Slot Status Configuration MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 67 Receive FIFO Range Filter Configuration Register (RFRFCFR) 0x009A Receive FIFO Range Filter Control Register (RFRFCTR) Dynamic Segment Status 0x009C Last Dynamic Transmit Slot Channel A Register (LDTXSLAR) 0x009E Last Dynamic Transmit Slot Channel B Register (LDTXSLBR) Protocol Configuration MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 68: Register Descriptions

    For some register fields, additional reset conditions exist. These additional reset conditions are mentioned in the detailed description of the register. The additional reset conditions are explained in Table 3-5. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 69: Table 3-5. Additional Register Reset Conditions

    The WMD bit controls the write mode. If the WMD bit is set to 0 during the write access, all fields of the internal register are updated. If the WMD bit set to 1, only the SEL field is MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 70: Figure 3-2. Module Version Register (Mvr)

    Write: MEN, SCM, CHB, CHA, BITRATE: Disabled Mode SFFE: Disabled Mode or POC:config CHA SFFE BITRATE Reset Figure 3-3. Module Configuration Register (MCR) This register defines the global configuration of the FlexRay module. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 71: Table 3-8. Mcr Field Descriptions

    PE channel 1 active ports RXD_BG1, TXD_BG1, and TXEN1# driven by FlexRay module ports RXD_BG2, TXD_BG2, and TXEN1# driven by FlexRay module PE channel 0 active PE channel 1 active Single Channel Device Mode MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 72: Figure 3-4. Strobe Signal Control Register (Stbscr)

    0. For more detailed and timing information refer to Section 3.4.16, “Strobe Signal Support”. NOTE In single channel device mode, channel B related strobe signals are undefined and should not be assigned to the strobe ports. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 73: Table 3-11. Stbscr Field Descriptions

    0x0F RXD_BG1 wakeup symbol decoded pulse 0x10 RXD_BG2 0x11 RXD_BG1 MTS or CAS symbol decoded pulse 0x12 RXD_BG2 0x13 RXD_BG1 frame decoded pulse 0x14 RXD_BG2 0x15 RXD_BG1 channel idle detected pulse 0x16 RXD_BG2 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 74 0x2F start of offset correction pulse MT start 0x30 cycle count[0] 0x31 cycle count[1] 0x32 cycle count[2] value MT start 0x33 cycle count[3] 0x34 cycle count[4] 0x35 cycle count[5] MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 75: Figure 3-5. Message Buffer Data Size Register (Mbdsr)

    Given in PE clock cycles Indicates internal PE event not directly related to FlexRay bus timing 3.3.2.6 Message Buffer Data Size Register (MBDSR) 0x000C Write: POC:config MBSEG2DS MBSEG1DS Reset Figure 3-5. Message Buffer Data Size Register (MBDSR) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 76: Figure 3-6. Message Buffer Segment Size And Utilization Register (Mbssutr)

    The message buffer search engine examines all individual message buffer with a message buffer number n less than or equaling LAST_MB_UTIL. Note: If LAST_MB_UTIL equals LAST_MB_SEG1 all individual message buffers belong to the first message buffer segment and the second message buffer segment is empty. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 77: Figure 3-7. Protocol Operation Control Register (Pocr)

    External Rate Correction Application — This field is used to trigger application of the external rate correction ERC_AP value defined in the Protocol Configuration Register 21 (PCR21) 00 do not apply external rate correction value 01 reserved 10 subtract external rate correction value 11 add external rate correction value MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 78: Figure 3-8. Global Interrupt Flag And Enable Register (Gifer)

    DEFAULT CONFIG state correctly. 3.3.2.9 Global Interrupt Flag and Enable Register (GIFER) 0x0016 Write: Normal Mode R MIF PRIF CHIF RBIF TBIF PRIE CHIE RBIE TBIE Reset Figure 3-8. Global Interrupt Flag and Enable Register (GIFER) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 79: Table 3-16. Gifer Field Descriptions

    Receive FIFO A Not empty interrupt if the FNEAIE flag is asserted. 0 Receive FIFO A is empty or interrupt is disabled 1 Receive FIFO A is not empty and interrupt enabled MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 80 1 Enable interrupt line Transmit Interrupt Enable — This flag controls if the transmit buffer interrupt line is asserted when the TBIF TBIE flag is set. 0 Disable interrupt line 1 Enable interrupt line MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 81: Figure 3-9. Protocol Interrupt Flag Register 0 (Pifr0)

    This is related to the MISSING_TERM event in the CSP process for offset correction in the FlexRay protocol. 0 No such event. 1 Insufficient number of measurements for offset correction detected. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 82 0 No such event 1 Timer 1 has reached its time limit Cycle Start Interrupt Flag — This flag is set when a communication cycle starts. CYS_IF 0 No such event 1 Communication cycle started. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 83: Figure 3-10. Protocol Interrupt Flag Register 1 (Pifr1)

    Odd Cycle Table Written Interrupt Flag — This flag is set if the FlexRay module has written the sync frame ODT_IF measurement / ID tables into the FlexRay Memory for the odd cycle. 0 No such event. 1 Sync frame measurement table written MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 84: Figure 3-11. Protocol Interrupt Enable Register 0 (Pier0)

    0 interrupt request generation disabled 1 interrupt request generation enabled pLatestTx Violation on Channel A Interrupt Enable — This bit controls LTXA_IF interrupt request generation. LTXA_IE 0 interrupt request generation disabled 1 interrupt request generation enabled MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 85: Figure 3-12. Protocol Interrupt Enable Register 1 (Pier1)

    0 interrupt request generation disabled 1 interrupt request generation enabled Protocol State Changed Interrupt Enable — This bit controls PSC_IF interrupt request generation. PSC_IE 0 interrupt request generation disabled 1 interrupt request generation enabled MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 86: Figure 3-13. Chi Error Flag Register (Chierfr)

    Protocol Operation Control Register (POCR) while the BSY flag is equal to 1. In this case the command is ignored by the FlexRay module and is lost. 0 No such error 1 POC command ignored MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 87 Protocol Configuration Register 24 (PCR24). 0 No such error occurred 1 Dynamic payload length error occurred MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 88: Figure 3-14. Message Buffer Interrupt Vector Register (Mbivec)

    MBIF and its interrupt enable bit MBIE asserted. If there is no receive message buffer with the interrupt status flag MBIF and the interrupt enable MBIE bits asserted, the value in this field is set to 0. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 89: Figure 3-15. Channel A Status Error Counter Register (Casercr)

    Field Description 15–0 Channel Status Error Counter — This field provides the current channel status error count. The counter STATUS_ERR_CNT value is updated within the first macrotick of the following slot or segment. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 90: Figure 3-17. Protocol Status Register 0 (Psr0)

    01 ALL_PENDING 10 ALL 11 reserved 10–8 Protocol State — protocol related variable: vPOC!State. This field indicates the state of the protocol. PROTSTATE POC:default config POC:config POC:wakeup POC:ready POC:normal passive POC:normal active POC:halt POC:startup MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 91: Figure 3-18. Protocol Status Register 1 (Psr1)

    101 COLLISION_UNKNOWN 110 TRANSMITTED 111 reserved 3.3.2.19 Protocol Status Register 1 (PSR1) 0x002A Additional Reset: CSAA, CSP, CPN: RUN Command Write: Normal Mode REMCSAT APTAC CSAA Reset Figure 3-18. Protocol Status Register 1 (PSR1) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 92: Figure 3-19. Protocol Status Register 2 (Psr2)

    Window and the clock synchronization. The NIT related status bits NBVB, NSEB, NBVA, and NSEA are updated by the FlexRay module after the end of the NIT and before the end of the first slot of the next MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 93: Table 3-27. Psr2 Field Descriptions

    STCA window on channel A This status bit is set if there was a transmission conflicts during the symbol window on channel A. 0 No such event 1 Transmission conflict detected MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 94: Figure 3-20. Protocol Status Register 3 (Psr3)

    1 to it. Writing a 0 does not change the flag state. If the application tries to clear a flag while the FlexRay module sets the flag at the same time, then that flag is not cleared. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 95: Table 3-28. Psr3 Field Descriptions

    Aggregated Content Error on Channel A — This flag is set when a content error has been detected on ACEA channel A. Content errors are detected in the communication slots, the symbol window, and the NIT. 0 No content error detected 1 Content error detected MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 96: Figure 3-21. Macrotick Counter Register (Mtctr)

    Cycle Counter — protocol related variable: vCycleCounter CYCCNT This field provides the number of the current communication cycle. If the counter reaches the maximum value of 63, the counter wraps and starts from zero again. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 97: Figure 3-23. Slot Counter Channel A Register (Sltctar)

    This register provides the sign extended rate correction value in microticks as it was calculated by the clock synchronization algorithm. The FlexRay module updates this register during the NIT of each odd numbered communication cycle. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 98: Figure 3-26. Offset Correction Value Register (Ofcorvr)

    Note: If the FlexRay module was not able to calculate an new offset correction term due to a lack of synchronization frames, the OFFSETCORR value is not updated. 3.3.2.28 Combined Interrupt Flag Register (CIFRR) 0x003C PRIF CHIF RBIF TBIF Reset Figure 3-27. Combined Interrupt Flag Register (CIFRR) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 99: Table 3-35. Cifrr Field Descriptions

    Configuration, Control, Status Registers (MBCCSRn) is equal to 1. 0 None of the individual transmit message buffers has the MBIF flag asserted. 1 At least one individual transmit message buffers has the MBIF flag asserted. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 100: Figure 3-28. Sync Frame Counter Register (Sfcntr)

    Figure 3-29. Sync Frame Table Offset Register (SFTOR) This register defines the Flexray Memory related offset for sync frame tables. For more details, see Section 3.4.12, “Sync Frame ID and Sync Frame Deviation Tables”. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 101: Figure 3-30. Sync Frame Table Configuration, Control, Status Register (Sftccsr)

    Tables for the odd cycle are valid. The FlexRay module clears this status bit when it starts updating the tables, and sets this bit when it has finished the table update. 0 Tables are not valid (update is ongoing) 1 Tables are valid (consistent). MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 102: Figure 3-31. Sync Frame Id Rejection Filter Register (Sfidrfr)

    9–0 Sync Frame Rejection ID — This field defines the frame ID of a frame that must not be used for clock SYNFRID synchronization. For details see Section 3.4.15.2, “Sync Frame Rejection Filtering”. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 103: Figure 3-32. Sync Frame Id Acceptance Filter Value Register (Sfidafvr)

    Filter Mask — This field defines the mask for the sync frame acceptance filtering. FMSK 3.3.2.35 Network Management Vector Registers (NMVR0–NMVR5) 0x004C (NMVR0) 0x004E (NMVR1) 0x0050 (NMVR2) 0x0052 (NMVR3) 0x0054 (NMVR4) 0x0056 (NMVR5) NMVP[15:8] NMVP[7:0] Reset Figure 3-34. Network Management Vector Registers (NMVR0–NMVR5) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 104: Table 3-42. Nmvr[0:5] Field Descriptions

    Table 3-44. NMVLR Field Descriptions Field Description 3–0 Network Management Vector Length — protocol related variable: gNetworkManagementVectorLength NMVL This field defines the length of the Network Management Vector in bytes. Legal values are between 0 and 12. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 105: Figure 3-36. Timer Configuration And Control Register (Ticcr)

    Timer T1 State — This status bit provides the current state of timer T1. T1ST 0 timer T1 is idle 1 timer T1 is running NOTE Both timers are deactivated immediately when the protocol enters a state different from POC:normal active POC:normal passive. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 106: Figure 3-37. Timer 1 Cycle Set Register (Ti1Cysr)

    Timer 1 Macrotick Offset — This field defines the macrotick offset value for timer 1. T1_MTOFFSET NOTE If the application modifies the value in this register while the timer is running, the change becomes effective immediately and timer T1 expires according to the changed value. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 107: Figure 3-39. Timer 2 Configuration Register 0 (Ti2Cr0)

    3.3.2.41 Timer 2 Configuration Register 1 (TI2CR1) 0x0062 Write: Any Time T2_MTOFFSET T2_MTCNT[15:0] Reset Figure 3-40. Timer 2 Configuration Register 1 (TI2CR1) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 108: Figure 3-41. Slot Status Selection Register (Sssr)

    SSSR3. Each internal registers selects a slot, or symbol window/NIT, whose status vector is saved in the corresponding Slot Status Registers (SSR0–SSR7) according to Table 3-51. For a detailed description of slot status monitoring, refer to Section 3.4.18, “Slot Status Monitoring”. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 109: Figure 3-42. Slot Status Counter Condition Register (Ssccr)

    Slot Status Counter Registers (SSCR0–SSCR3). The correspondence is given in Table 3-53. For a detailed description of slot status counters, refer to Section 3.4.18.4, “Slot Status Counter Registers”. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 110: Table 3-52. Ssccr Field Descriptions

    STATUSMASK[0] – This bit enables the counting for slots with the transmission conflict indicator bit set to 1. Table 3-53. Mapping between internal SSCCRn and SSCRn Condition Register Condition Defined for Register SSCCR0 SSCR0 SSCCR1 SSCR1 SSCCR2 SSCR2 SSCCR3 SSCR3 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 111: Figure 3-43. Slot Status Registers (Ssr0-Ssr7)

    B vSS!ContentError vSS!ContentError Boundary Violation on Channel B — protocol related variable: vSS!BViolation channel B vSS!BViolation vSS!BViolation Transmission Conflict on Channel B — protocol related variable: vSS!TxConflict channel B vSS!TxConflict vSS!TxConflict MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 112: Figure 3-44. Slow Status Counter Registers (Sscr0-Sscr3)

    The provided value depends on the control bits and fields in the related internal slot status counter condition register SSCCRn, which can be programmed by using the Slot Status Counter Condition Register (SSCCR). For more details, see Section 3.4.18.4, “Slot Status Counter Registers”. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 113: Figure 3-45. Mts A Configuration Register (Mtsacfr)

    Cycle Counter Value — This field provides the filter value for the MTS cycle count filter. CYCCNTVAL 3.3.2.47 MTS B Configuration Register (MTSBCFR) 0x0082 Write: MTE: Any Time CYCCNTMSK, CYCCNTVAL: POC:config CYCCNTMSK CYCCNTVAL Reset Figure 3-46. MTS B Configuration Register (MTSBCFR) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 114: Figure 3-47. Receive Shadow Buffer Index Register (Rsbir)

    FlexRay module: Updates the message buffer header index after successful reception. Application: Provides initial message buffer header index. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 115: Figure 3-48. Receive Fifo Selection Register (Rfsr)

    Start Index — This field defines the number of the message buffer header field of the first message buffer of the SIDX selected receive FIFO. The FlexRay module uses the value of the SIDX field to determine the physical location of the receiver FIFO’s first message buffer header field. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 116: Figure 3-50. Receive Fifo Depth And Size Register (Rfdsr)

    If the receive FIFO not empty flag FNEAIF is not set, the RDIDX field points to a physical message buffer that contains invalid data. Only when FNEAIF is set, does the message buffer indicated by RDIDX contain valid data. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 117: Figure 3-52. Receive Fifo B Read Index Register (Rfbrir)

    ID filtering see Section 3.4.9.5, “Receive FIFO filtering”. Table 3-65. RFMIDAFVR Field Descriptions Field Description 15–0 Message ID Acceptance Filter Value — Filter value for the message ID acceptance filter. MIDAFVAL MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 118: Figure 3-54. Receive Fifo Message Id Acceptance Filter Mask Register (Rfmiafmr)

    Figure 3-56. Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR) This register defines the filter mask for the frame ID rejection filter of the selected receive FIFO. For details on frame ID filtering see Section 3.4.9.5, “Receive FIFO filtering”. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 119: Figure 3-57. Receive Fifo Range Filter Configuration Register (Rfrfcfr)

    Figure 3-58. Receive FIFO Range Filter Control Register (RFRFCTR) This register is used to enable and disable each frame ID range filter and to define whether it is running as acceptance or rejection filter. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 120: Figure 3-59. Last Dynamic Slot Channel A Register (Ldtxslar)

    Number of the last transmission slot in the dynamic segment for channel A. If no frame was transmitted during SLOTA the dynamic segment on channel A, the value of this field is set to 0. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 121: Figure 3-60. Last Dynamic Slot Channel B Register (Ldtxslbr)

    μT noise_listen_timeout (gListenNoise * pdListenTimeout) - 1 16/17 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 122 - pdMaxDrift 24/25 μT micro_per_cycle_max pMicroPerCycle + pdMaxDrift 26/27 μT micro_per_macro_nom_half round(pMicroPerMacroNom / 2) μT offset_correction_out pOffsetCorrectionOut μT rate_correction_out pRateCorrectionOut single_slot_enabled pSingleSlotEnabled bool wakeup_channel pWakeupChannel Table 3-74 wakeup_pattern pWakeupPattern number μT decoding_correction_a pDecodingCorrection pDelayCompensation[A] MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 123: Figure 3-61. Protocol Configuration Register 0 (Pcr0)

    Protocol Configuration Register 1 (PCR1) 0x00A2 Write: POC:config macro_after_first_static_slot Reset Figure 3-62. Protocol Configuration Register 1 (PCR1) 3.3.2.62.3 Protocol Configuration Register 2 (PCR2) 0x00A4 Write: POC:config minislot_after_action_point number_of_static_slots Reset Figure 3-63. Protocol Configuration Register 2 (PCR2) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 124: Figure 3-64. Protocol Configuration Register 3 (Pcr3)

    Protocol Configuration Register 6 (PCR6) 0x00AC Write: POC:config symbol_window_after_action_point macro_initial_offset_a Reset Figure 3-67. Protocol Configuration Register 6 (PCR6) 3.3.2.62.8 Protocol Configuration Register 7 (PCR7) 0x00AE Write: POC:config decoding_correction_b micro_per_macro_nom_half Reset Figure 3-68. Protocol Configuration Register 7 (PCR7) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 125: Figure 3-69. Protocol Configuration Register 8 (Pcr8)

    Figure 3-71. Protocol Configuration Register 10 (PCR10) 3.3.2.62.12 Protocol Configuration Register 11 (PCR11) 0x00B6 Write: POC:config R key_ key_ slot_ slot_ used_ used_ offset_correction_start for_ for_ start sync Reset Figure 3-72. Protocol Configuration Register 11 (PCR11) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 126: Figure 3-73. Protocol Configuration Register 12 (Pcr12)

    3.3.2.62.16 Protocol Configuration Register 15 (PCR15) 0x00BE Write: POC:config listen_timeout[15:0] Reset Figure 3-76. Protocol Configuration Register 15 (PCR15) 3.3.2.62.17 Protocol Configuration Register 16 (PCR16) 0x00C0 Write: POC:config macro_initial_offset_b noise_listen_timeout[24:16] Reset Figure 3-77. Protocol Configuration Register 16 (PCR16) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 127: Figure 3-78. Protocol Configuration Register 17 (Pcr17)

    0x00C8 Write: POC:config micro_initial_offset_b micro_initial_offset_a Reset Figure 3-81. Protocol Configuration Register 20 (PCR20) 3.3.2.62.22 Protocol Configuration Register 21 (PCR21) 0x00CA Write: POC:config extern_rate_ latest_tx correction Reset Figure 3-82. Protocol Configuration Register 21 (PCR21) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 128: Figure 3-83. Protocol Configuration Register 22 (Pcr22)

    Reset Figure 3-86. Protocol Configuration Register 25 (PCR25) 3.3.2.62.27 Protocol Configuration Register 26 (PCR26) 0x00D4 Write: POC:config R allow _halt_ micro_per_cycle_max comp_accepted_startup_range_b [19:16] _to_ clock Reset Figure 3-87. Protocol Configuration Register 26 (PCR26) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 129: Figure 3-88. Protocol Configuration Register 27 (Pcr27)

    3.3.2.62.30 Protocol Configuration Register 29 (PCR29) 0x00DA Write: POC:config extern_offset_ minislots_max correction Reset Figure 3-90. Protocol Configuration Register 29 (PCR29) 3.3.2.62.31 Protocol Configuration Register 30 (PCR30) 0x00DC Write: POC:config sync_node_max Reset Figure 3-91. Protocol Configuration Register 30 (PCR30) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 130: Figure 3-92. Message Buffer Configuration, Control, Status Registers (Mbccsrn)

    EDS status bit is 1. 0 No effect 1 message buffer enable/disable triggered Note: If the application writes 1 to this bit, the write access to all other bits is ignored. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 131 Additionally this flag is set immediately when a transmit message buffer was enabled. 0 slot status not updated 1 slot status updated / message buffer recently enabled Writing a 1 clears this flag. Writing a 0 does not change the flag state. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 132: Figure 3-93. Message Buffer Cycle Counter Filter Registers (Mbccfrn)

    A transmit on channel A store first valid frame store first valid frame received on channel A received on channel A no frame transmission no frame transmission no frame stored no frame stored MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 133: Figure 3-94. Message Buffer Frame Id Registers (Mbfidrn)

    The application writes the index of the initially associated message buffer header field into this register. The FlexRay module updates this register after frame reception or transmission. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 134: Functional Description

    16-bit aligned. 3.4.2.1.1 Frame Header The frame header occupies the first six bytes in the message buffer header field. It contains all FlexRay frame header related information according to the FlexRay Communications System Protocol MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 135: Message Buffer Types

    Each individual message buffer consists of two parts, the physical message buffer, which is located in the FRM, and the message buffer control data, which are located in dedicated registers. The structure of an individual message buffer is given in Figure 3-97. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 136: Figure 3-97. Individual Message Buffer Structure

    2 * MBDSR.MBSEG1DS bytes • the minimum length of the message buffer data field for individual message buffers assigned to the second segment is 2 * MBDSR.MBSEG2DS bytes. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 137: Figure 3-98. Receive Shadow Buffer Structure

    A receive FIFO consists of a set of physical message buffers in the FRM and a set of receive FIFO control registers located in dedicated registers. The structure of a receive FIFO is given in Figure 3-99. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 138: Figure 3-99. Receive Fifo Structure

    Frame Header[i] Data Field Offset[i] Slot Status[i] SADR_MBHF[1] Frame Header[1] Data Field Offset[1] Slot Status[1] Message Buffer Header Fields RFDSR[A] RFSIR[A] RFARIR RFDSR[B] RFSIR[B] RFBRIR Receive FIFO Control Register Figure 3-99. Receive FIFO Structure MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 139 Individual Message Buffer Control Data During normal operation, each individual message buffer can be controlled by the control and trigger bits CMT, LCKT, EDT, and MBIE in the Message Buffer Configuration, Control, Status Registers (MBCCSRn). MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 140: Flexray Memory Layout

    The FRM starts at modue address 0x800. The FRM contains three areas: the message buffer header area, the message buffer data area, and the sync frame table area. The areas are described in this section. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 141: Figure 3-100. Example Of Frm Layout

    3.4.4.2 Message Buffer Data Area The message buffer data area contains all the message buffer data fields of the physical message buffers. Each message buffer data field must start at a 16-bit boundary. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 142: Physical Message Buffer Description

    The frame header is read out when the frame is transferred to the FlexRay bus. The structure of the frame header in the message buffer header field is given in Figure 3-101. A detailed description of the frame header fields is given in Table 3-81. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 143: Figure 3-101. Frame Header Structure

    The PE generates a syntactically and semantically correct frame with payload_length_static payload words and the payload length field in the frame header set to payload_length_static. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 144: Table 3-81. Frame Header Field Descriptions

    ID error flag FID_EF in the CHI Error Flag Register (CHIERFR). The value of the FID field is ignored and replaced by the value provided in the Message Buffer Frame ID Registers (MBFIDRn). MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 145 FIFOs. The content of the slot status structure for receive message buffers depends on the message buffer type and on the channel assignment for individual receive message buffers as given by Table 3-82. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 146: Figure 3-102. Receive Message Buffer Slot Status Structure (Chab)

    B vRF!Header!SyFIndicator vRF!Header!SyFIndicator Null Frame Indicator Channel B — protocol related variable: vRF!Header!NFIndicator channel B vRF!Header!NFIndicator vRF!Header!NFIndicator Startup Frame Indicator Channel B — protocol related variable: vRF!Header!SuFIndicator channel B vRF!Header!SuFIndicator vRF!Header!SuFIndicator MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 147 All other status bits in this structure are related to a receive process that may have occurred. The content of the slot status structure for transmit message buffers depends on the channel assignment as given by Table 3-84. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 148: Figure 3-105. Transmit Message Buffer Slot Status Structure (Chab)

    B vRF!Header!SuFIndicator vRF!Header!SuFIndicator Syntax Error on Channel B — protocol related variable: vSS!SyntaxError channel B vSS!SyntaxError vSS!SyntaxError Content Error on Channel B — protocol related variable: vSS!ContentError channel B vSS!ContentError vSS!ContentError MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 149: Table 3-86. Message Buffer Data Field Minimum Length

    Individual Message Buffer in Segment 1 MBDSR.MBSEG1DS Receive Shadow Buffer in Segment 1 MBDSR.MBSEG1DS Individual Message Buffer in Segment 2 MBDSR.MBSEG2DS Receive Shadow Buffer in Segment 2 MBDSR.MBSEG2DS Receive FIFO for channel A RFDSR.ENTRY_SIZE (RFSR.SEL = 0) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 150: Figure 3-108. Message Buffer Data Field Structure

    For receive message buffers, receive shadow buffers, and receive FIFOs, the application must not write to the message buffer data field. For transmit message buffers, the application must follow the write access restrictions given in Table 3-87. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 151: Individual Message Buffer Functional Description

    The application configures the number of utilized individual message buffers by writing the message buffer number of the last utilized message buffer into the LAST_MB_UTIL field in the Message Buffer Segment Size and Utilization Register (MBSSUTR). MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 152: Table 3-89. Individual Message Buffer Types

    A single transmit message buffer is used by the application to provide message data to the FlexRay module transmitted over the FlexRay Bus. The FlexRay module uses the transmit message buffers to provide MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 153: Figure 3-109. Single Transmit Message Buffer Access Regions

    Message Buffer Search The trigger bits MBCCSRn.EDT and MBCCSRn.LCKT, and the interrupt enable bit MBCCSRn.MBIE are not under access control and can be accessed from the application at any time. The status bits MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 154: Figure 3-110. Single Transmit Message Buffer States

    Excluded from message buffer search. HDisLck – Disabled and Locked - Message Buffer under configuration. Excluded from message buffer search. HLck Locked - Applications access to data, control, and status. Included in message buffer search. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 155: Table 3-92. Single Transmit Message Buffer Application Transitions

    CHI Error Flag Register (CHIERFR) is set. Table 3-92. Single Transmit Message Buffer Application Transitions Transition Command Condition Description MBCCSRn.EDS = 0 Application triggers message buffer enable. MBCCSRn.EDT:= 1 MBCCSRn.EDS = 1 Application triggers message buffer disable. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 156: Table 3-93. Single Transmit Message Buffer Module Transitions

    Idle, HLck SA > HD Slot Assigned > Message Buffer Disable MA > HD Message Available > Message Buffer Disable CCMa TX > HL Transmission Start > Message Buffer Lock MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 157 3-111. In this example, the message buffer with message buffer number n is Idle at the start of the Figure search slot, matches the slot and cycle number of the next slot, and message buffer data are valid, MBCCSRn.CMT equals 1. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 158: Figure 3-111. Message Transmission Timing

    As a result of the message buffer search described in Section 3.4.7, “Individual Message Buffer Search”, the FlexRay module triggers the slot assigned transition SA for up to two transmit message buffers if at MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 159: Figure 3-113. Null Frame Transmission From Idle State

    Because the null frame transmission does not use the message buffer data, the application can lock/unlock the message buffer during null frame transmission. A transmit message buffer timing and state change diagram for null frame transmission for this case is given in Figure 3-116. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 160: Figure 3-116. Null Frame Transmission From Idle State With Locking

    In any of these two cases, the status of the message buffer is not changed at all with the SU transition. The slot status field is not updated, the status and control flags are not changed, and the interrupt flag is not set. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 161: Figure 3-117. Receive Message Buffer Access Regions

    Message Buffer Header Field: Data Field Offset Message Buffer Header Field: Frame Header Message Buffer Header Field: Slot Status Message Buffer Data Field: DATA[0-N] MBIDXRn.MBIDX MBCCSRn.DVAL/DUP MBCCSRn.MTD MBCCFRn.CHA/CHB/CCF* MBFIDRn.FID Figure 3-117. Receive Message Buffer Access Regions MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 162: Figure 3-118. Receive Message Buffer States

    Access from State Description LCKS Appl. Module Idle – Idle - Message Buffer is idle. Included in message buffer search. HDis – Disabled - Message Buffer under configuration. Excluded from message buffer search. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 163: Table 3-97. Receive Message Buffer Application Transitions

    MBCCSRn.EDS = 0 Application triggers message buffer enable. MBCCSRn.EDT:= 1 MBCCSRn.EDS = 1 Application triggers message buffer disable. MBCCSRn.LCKS = 0 Application triggers message buffer lock. MBCCSRn.LCKT:= 1 MBCCSRn.LCKS = 1 Application triggers message buffer unlock. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 164: Table 3-98. Receive Message Buffer Module Transitions

    • minislot start, in the dynamic frame segment • NIT start The filters that are used for the search are described in Section 3.4.7.1, “Individual Message Buffer Filtering”. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 165: Table 3-100. Receive Message Buffer Update

    - MBIF:= 1 Valid null frame received. - Message Buffer Data Field not updated. - Frame Header Field not updated. - Slot Status Field updated. - DUP:= 0 - DVAL not changed - MBIF:= 1 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 166: Figure 3-119. Message Reception Timing

    2*MBDSR.MBSEG1DS, the FlexRay module writes only the received number of bytes and does not change the trailing bytes in the message buffer data field of the receive shadow buffer. The same holds for the message buffer segment 2 with MBDSR.MBSEG2DS. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 167 One side is called the commit side and is accessed by the application to provide the message data. The other side is called the transmit side and is used by the MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 168: Figure 3-120. Double Transmit Buffer Structure And Data Flow

    Message Buffer Data Field: DATA[0-N] Message Buffer Data Field: DATA[0-N] Message Buffer Header Field: Slot Status Message Buffer Header Field: Slot Status MBCCSR[2n].MBT/MTD MBCCSR[2n+1].MBT/MTD MBCCFR[2n].MTM/CHA/CHB/CCF* MBCCFR[2n+1].MTM/CHA/CHB/CCF* MBFIDR[2n].FID MBFIDR[2n+1].FID Figure 3-121. Double Transmit Message Buffer Access Regions Layout MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 169: Table 3-101. Double Transmit Message Buffer Access Regions Description

    The status bits MBCCSRn.EDS and MBCCSRn.LCKS provide the application with the required message buffer status information. The internal status information is not visible to the application. 3.4.6.4.2 Message Buffer States This section describes the transmit message buffer states and provides a state diagram. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 170: Figure 3-122. Double Transmit Message Buffer State Diagram (Commit Side)

    Disabled and Locked - Message Buffer under configuration. Commit Side can not be used for internal message transfer. HLck Locked - Applications access to data, control, and status. Commit Side can not be used for internal message transfer. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 171: Figure 3-123. Double Transmit Message Buffer State Diagram (Transmit Side)

    Message Buffer Data transferred from commit side to transmit side. CCTx – Message Transmission - Message buffer data transmit. Payload data from buffer transmitted MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 172: Table 3-104. Double Transmit Message Buffer Host Transitions

    Table 3-105. The transitions C1 and C2 apply to both sides of the message buffer and are applied at the same time. All other FlexRay module transitions apply to the transmit side only. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 173: Table 3-105. Double Transmit Message Buffer Module Transitions

    Internal Message Transfer Start > Message Buffer Lock module internal Idle MA > SA Message Available > Slot Assigned CCMa TX > STS Transmission Slot Start > Static Slot Start TX > DSS Transmission Slot Start > Dynamic Slot Start MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 174 The transmit side is in one of the states idle, CCSa, or CCMa • The transmit side contains no valid message data, MBCCSR[2n+1].CMT equals 0, or the message data was transmitted at least once, MBCCSR[2n+1].DVAL equals 1 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 175: Figure 3-124. Internal Message Transfer In Streaming Commit Mode

    CCITx Idle HLck Idle Idle HLck internal message transfer overwrites non-transmitted message CCITx CCITx Idle Idle Idle search[s+1] slot s slot s+1 slot s+2 Figure 3-125. Internal Message Transfer in Immediate Commit Mode MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 176: Individual Message Buffer Search

    If all message buffers assigned or subscribed to the next slot are assigned to both channels, only one sorted list of matching message buffers is created. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 177: Table 3-107. Message Buffer Search Priority

    In case of a transmit message buffer, though, this buffer is added to the matching message buffer list with MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 178: Individual Message Buffer Reconfiguration

    A reconfiguration does not change the basic type of the individual message buffer, if both the message buffer transfer direction bit MBCCSn.MTD and the message buffer type bit MBCCSn.MBT are not changed. This type of reconfiguration is denoted by RC1 in Figure 3-127. Single transmit and receive MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 179: Receive Fifo

    The index of the first FIFO entry given by Receive FIFO Start Index Register (RFSIR) • The number of FIFO entries and the length of each FIFO entry as given by Receive FIFO Depth and Size Register (RFDSR) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 180 Section 3.4.3.3, “Receive FIFO”. When the application has read all message buffer data and status information, it writes 1 to the fifo not-empty interrupt flags FNEAIF or MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 181 The FIFO does not receive invalid or null-frames. For each FIFO filter, the pass criteria is specified in the related section given below. Only frames that have passed all filters are appended to the FIFO. The FIFO filter path is depicted in Figure 3-128. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 182: Figure 3-128. Received Frame Fifo Filter Path

    Consequently, a received valid frame with the frame ID FID passes the RX FIFO Frame ID Value-Mask Rejection Filter if Equation 3-10 is fulfilled. ∧ ≠ ∧ Eqn. 3-10 RFFIDRFMR FIDRFMSK RFFIDRFVR FIDRFVAL RFFIDRFMR FIDRFMSK MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 183 Acceptance Filter Mask Register (RFMIAFMR). This filter applies only to valid frames received in the dynamic segment with the payload preamble indicator bit PPI set to 1. All other frames pass this filter. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 184: Channel Device Modes

    RXD_BG1, TXD_BG1, and TXEN1# and can be connected to the physical bus channel A (shown in Figure 3-130) or the physical bus channel B (shown in Figure 3-131). MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 185: Figure 3-130. Single Channel Device Mode (Channel A)

    FlexRay Bus Driver TXD_BG1 channel A Channel A TXEN1# cfg(A) Init Value for Frame CRC is cCrcInit[B] cCrcInit[A] RXD_BG2 reg(B) TXD_BG2 channel B TXEN2# cfg(B) cCrcInit[B] Figure 3-131. Single Channel Device Mode (Channel B) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 186: External Clock Synchronization

    FRM and ensures application access to consistent tables by means of table locking. After the application has locked the table successfully, the FlexRay module does not overwrite these tables and the application can read a consistent snapshot. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 187: Figure 3-134. Sync Table Memory Layout

    Sync Deviation ChB 14 Sync Deviation ChB 14 Offset + $3A Sync Frame ID ChB 15 Sync Frame ID ChB 15 Sync Deviation ChB 15 Sync Deviation ChB 15 Figure 3-134. Sync Table Memory Layout MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 188: Table 3-108. Sync Frame Table Generation Modes

    SFTCCSR.ELKT. When the even table is not currently updated by the FlexRay module, the lock is granted and the even table lock status bit SFTCCSR.ELKS is set. This indicates that the application has successfully locked the even sync tables and the corresponding status information fields SFRA, SFRB in MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 189: Mts Generation

    The application can configure the set of communication cycles in which the MTS is transmitted over the FlexRay bus by programming the CYCCNTMSK and CYCCNTVAL fields in the MTS A Configuration Register (MTSACFR) MTS B Configuration Register (MTSBCFR). MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 190: Sync Frame And Startup Frame Transmission

    Sync Frame and Startup Frame Transmission in POC:normal active In the POC:normal active state, the sync and startup frame transmission depends on the message buffer setup. If at least one of the indication bits PCR11.key_slot_used_for_sync or MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 191: Sync Frame Filtering

    MCR SFFE Eqn. 3-22 ] SFIDRFR SYNFRID 9:0 ≠ FID 9:0 Eqn. 3-23 NOTE Sync frames are transmitted in the static segment only. Thus FID is less than or equal to 1023. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 192: Strobe Signal Support

    These signals are listed in Table 3-12 with a positive clock offset. An example waveform is given Figure 3-137. PE Clock Strobe Signal FlexRay Bus Event Figure 3-137. Strobe Signal Timing (type = pulse, clk_offset = +4) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 193: Timer Support

    Configuration Register 0 (TI2CR0) Timer 2 Configuration Register 1 (TI2CR1), has expired since the trigger or restart of timer 2. The relative timer is implemented as a down counter and expires when it has MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 194: Slot Status Monitoring

    1 static segment dynamic segment symbol window communication cycle Figure 3-138. Slot Status Vector Update NOTE The slot status for the NIT of cycle n is provided after the start of cycle n+1. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 195: Table 3-109. Slot Status Content

    NIT are taken into account. The counters wrap round after they have reached the maximum value. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 196: Figure 3-139. Slot Status Counting And Sscrn Update

    The increment condition for each slot status counter consists of two parts, the frame related condition part and the slot related condition part. The internal slot status counter SSCRn_INT is incremented if at least one of the conditions is fulfilled: 1. frame related condition: MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 197: Interrupt Support

    Each individual message buffer provides an interrupt flag MBCCSn.MBIF and an interrupt enable bit MBCCSn.MBIE. The FlexRay module sets the interrupt flag when the slot status of the message buffer was updated. If the interrupt enable bit is asserted, an interrupt request is generated. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 198 3.4.19.2.3 Protocol Interrupt The combined protocol interrupt request PRTIRQ is generated when at least one of the individual protocol interrupt sources generates an interrupt request and the interrupt enable bit GIFER.PRIE is set. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 199 GIFER.CHIE is set. 3.4.19.2.5 Module Interrupt The combined module interrupt request MIRQ is generated if at least one of the combined interrupt sources generates an interrupt request and the interrupt enable bit GIFER.MIE is set. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 200: Figure 3-140. Scheme Of Cascaded Interrupt Request

    & & GIFER.TBIE Transmit GIFER.CHIF CHIIRQ GIFER.PRIF PRTIRQ & GIFER.PRIE GIFER.FNEAIF FNEAIRQ & GIFER.FNEAIE GIFER.FNEBIF FNEBIRQ & GIFER.FNEBIE GIFER.WUPIF WUPIRQ & GIFER.WUPIE GIFER.MIF MIRQ & GIFER.MIE Figure 3-140. Scheme of cascaded interrupt request MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 201: Figure 3-141. Int_Cc# Generation Scheme

    Combined Interrupt Flags n = # Message Buffers MBCCSRn.MTD CIFR.TBIF & MBCCSRn.MBIF Transmit CIFR.RBIF & Receive CHIER[15:0] CIFR.CHIF PIFR0[15:0] CIFR.PRIF PIFR1[15:0] CIFR.MIF GIFER.FNEAIF GIFER.FNEBIF GIFER.WUPIF CIFR.FNEAIF CIFR.FNEBIF CIFR.WUPIF Figure 3-142. Scheme of combined interrupt flags MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 202: Clock Domain Crossing

    The bit rate of 8 Mbit/s is not defined by the FlexRay Communications System Protocol Specification, Version 2.1 Rev A. Initialization Information This section provides information for initializing and using the FlexRay module. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 203: Flexray Initialization Sequence

    This search must be finished within one FlexRay slot. The shortest FlexRay slot is an empty dynamic slot. An empty dynamic slot is a minislot and consists of gdMinislot MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 204: Application Information

    HALT command to the PE using the Protocol Operation Control Register (POCR). The PE then waits for the end of the communication cycle and goes into the POC:halt MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 205: Protocol Control Command Execution

    PE detects a fatal protocol error, some commands already stored in the command vector are removed from this vector. Table 3-112. Protocol Control Command Priorities Protocol Command Priority Interrupted By Cleared and Terminated By RESET (highest) 1 FREEZE RESET none READY RESET CONFIG_COMPLETE RESET MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 206: Protocol Reset Command

    Protocol Operation Control Register (POCR), until the freeze bit FRZ bit in Protocol Status Register 1 (PSR1) is cleared and the PROTSTATE field in Protocol Status Register 0 (PSR0) is set to DEFAULT_CONFIG. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 207: Port Integration Module (Pim)

    This is a high level description only; detailed descriptions of operating modes are contained in later sections. External Signal Description For detailed descriptions of particular pins and signals, refer to Section 2.4, “Signal Descriptions”. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 208: Functional Mode

    Controller clock output selectable between disabled, Output 4/10/40 MHz Other RESET# Hardware reset input Input INT_CC# Controller interrupt output Output DC/OD TEST Factory Test mode select — must be tied to logic low in Input application MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 209: Reset Mode

    Part ID Register (PIDR) 0x00F2 ASIC Version Number Register (AVNR) 0x00F4 Host Interface Pins Drive Strength Register (HIPDSR) 0x00F6 Physical Layer Pins Drive Strength Register (PLPDSR) 0x00F8 Host Interface Pins Pullup/pulldown Enable Register (HIPPER) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 210: Port Integration Module Registers

    Address in MFR4310 = 0x00F4 Write: Any Time Reset Figure 4-3. Host Interface Pins Drive Strength Register (HIPDSR) This register controls the drive strength of the host interface, interrupt, debug, and output clock pins. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 211: Figure 4-4. Physical Layer Pins Drive Strength Register (Plpdsr)

    0 Pin drive strength is reduced to 1/3 of full strength 1 Pin drive strength is full Transmit data (channel B) output drive strength control TXD_BG2 0 Pin drive strength is reduced to 1/3 of full strength 1 Pin drive strength is full MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 212: Figure 4-5. Host Interface Pins Pullup/Pulldown Enable Register (Hipper)

    AMI/MPC output enable / HCS12 address select bit 0 pullup/pulldown enable OE#/ACS0 0 pullup/pulldown disabled 1 pullup/pulldown enabled AMI/MPC address bit 11 / HCS12 address select bit 1 pullup/pulldown enable A11/ACS1 0 pullup/pulldown disabled 1 pullup/pulldown enabled MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 213: Figure 4-6. Host Interface Pins Pullup/Pulldown Control Register (Hippcr)

    AMI/MPC address bit 4 / HCS12 expanded address bit 16 pullup/pulldown control A4/XADDR16 0 pulldown 1 pullup AMI/MPC address bit 5 / HCS12 expanded address bit 15 pullup/pulldown control A5/XADDR15 0 pulldown 1 pullup MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 214: Figure 4-7. Physical Layer Pins Pullup/Pulldown Enable Register (Plpper)

    Physical Layer Pins Pullup/pulldown Enable Register (PLPPER) Address in MFR4310 = 0x00FC Write: Any Time Reset Figure 4-7. Physical Layer Pins Pullup/pulldown Enable Register (PLPPER) This register enables/disables the pullups/pulldowns of the FlexRay physical layer pins. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 215: Functional Description

    Pin multiplexing and pin configuration constraints for reset mode 4.4.1 Functional Mode In functional mode, the Port Integration Module controls the functional interface: • Host Interface • Physical Layer Interface • Clock Interface MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 216: Reset Mode

    Table 4-10. Reset Mode Interface Name Direction Special Configuration TXD_BG2/IF_SEL0 Input TXD_BG1/IF_SEL1 Input DBG[3:2]/CLK_S[1:0] Input Section 4.2.2, “Reset Mode” and Chapter 6, “Clocks and Reset Generator (CRG)” for reset mode details. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 217: Dual Output Voltage Regulator (Vreg3V3V2)

    Block Diagram Figure 5-1 shows the function principle of VREG3V3V2 by means of a block diagram. The regulator core REG consists of two parallel sub-blocks, REG1 and REG2, providing two independent output voltages. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 218: Figure 5-1. Vreg3V3 Block Diagram

    Dual Output Voltage Regulator (VREG3V3V2) DDOSC REG2 SSOSC DD2_5 REG1 SS2_5 CTRL REG: Regulator Core CTRL: Regulator Control LVR: Low Voltage Reset POR: Power-on Reset Figure 5-1. VREG3V3 Block Diagram MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 219: External Signal Description

    Internal precision reference circuits are supplied from these signals. A chip external decoupling capacitor (100 nF 220 nF, X7R ceramic) between V and V can further improve the quality of this … supply. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 220: Vddosc , V Ssosc - Regulator Output2 (Osc)

    , the signal goes low. The transition to low forces the CPU into the power-on sequence. PORD Due to its role during chip power-up, this module must be active in all operating modes of VREG3V3V2. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 221: Lvr - Low Voltage Reset

    . Then POR becomes low and the reset generator of the device DD2_5 PORD continues the start-up sequence. 5.4.2 Low Voltage Reset For information on low-voltage reset see Section 5.3.4, “LVR — Low Voltage Reset”. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 222 Dual Output Voltage Regulator (VREG3V3V2) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 223: Clocks And Reset Generator (Crg)

    Controllable system reset generation under low quality clock situations (clock monitor) • System reset indication • Host interface selection • Control signals selection for CLKOUT clock output • System clocks generation • Reset glitch filter MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 224: Mfr4310 Relevant Pins For The Crg

    The bits in the CRG registers are set by the CRG synchronous to the CHI clock signal. The system reset signal is a hard reset for CRG registers. 6.3.1 Detection Enable Register (DER) Address in MFR4310 = 0x00E0 Write: Any Time CMIE Reset Figure 6-1. Detection Enable Register (DER) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 225: Clock And Reset Status Register (Crsr)

    CLK_S[1:0] pins. Table 2-5 for coding. NOTE On a power-on or low-voltage reset, CMIF and PRIF are both cleared to 0. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 226: Functional Description

    CRSR.PRIF, on the rising edge of the power-on reset signal. NOTE The CRG deasserts the INT_CC# signal when the CRSR.PRIF, CRSR.LVIF, CRSR.CMIF and CRSR.ERIF bits are 0. Figure 6-3 illustrates the power-on reset situation. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 227: Figure 6-3. Crg Power On Reset

    The CRG deasserts the INT_CC# signal when the CRSR.PRIF, CRSR.LVIF, CRSR.CMIF and CRSR.ERIF bits are 0. Figure 6-4 Figure 6-5 show the operations performed by the CRG when a low voltage reset or a clock monitor failure (if enabled) signal occurs. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 228: Figure 6-4. Low Voltage Reset

    The CRG asserts the INT_CC# interrupt line and the external reset interrupt flag, CRSR.ERIF, on the assertion of the RESET# signal. NOTE The CRG deasserts the INT_CC# signal when CRSR.PRIF, CRSR.LVIF, CRSR.CMIF and CRSR.ERIF bits are 0. Figure 6-6 illustrates an external reset scheme. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 229: Interface Selection

    The interface selection is made upon the levels on the bus signal IF_SEL[1:0] while a power-on, low voltage, clock monitor (if enabled) or external reset process is ongoing. The CRG latches the IF_SEL[1:0] during the latching window as presented in Figure 6-7 Figure 6-8. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 230: Clkout Mode Selection And Control

    6.4.3 CLKOUT Mode Selection and Control The CLKOUT mode selection is done when the DBG[3:2]/CLK_S[1:0] pins are in the CLK_S[1:0] mode. In the DBG[3:2] modes the pads are outputs from the MFR4310 device. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 231: Figure 6-9. Clkout Mode Selection And Control During Low-Voltage Reset Or

    CLK_S[1:0] ~16380 EXTAL/CLK_CC periods ~16410 EXTAL/CLK_CC periods CLKOUT ~16420 EXTAL/CLK_CC periods system reset Figure 6-9. CLKOUT Mode Selection and Control during Low-voltage Reset or Clock Monitor Failure MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 232: Figure 6-10. Clkout Mode Selection And Control During External Reset

    Clocks and Reset Generator (CRG) Latching window RESET# CLK_S[1:0] ~30 EXTAL/CLK_CC periods ~60 EXTAL/CLK_CC periods CLKOUT ~70 EXTAL/CLK_CC periods system reset Figure 6-10. CLKOUT Mode Selection and Control during External Reset MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 233: Figure 6-11. Clkout Mode Selection And Control During Power-On Reset

    Clocks and Reset Generator (CRG) Latching window power-on reset CLK_S[1:0] ~16380 EXTAL/CLK_CC periods ~16410 EXTAL/CLK_CC periods CLKOUT ~16420 EXTAL/CLK_CC periods system reset Figure 6-11. CLKOUT Mode Selection and Control during Power-on Reset MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 234 Clocks and Reset Generator (CRG) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 235: Oscillator (Oscv2)

    These pins provide the interface for a crystal or a CMOS compatible clock to control the internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator amplifier. XTAL MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 236: Memory Map And Register Definition

    All internal system clocks are derived from the EXTAL input frequency. NOTE Freescale Semiconductor recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier The Crystal circuit is changed from standard.

  • Page 237: Electrical Characteristics

    Parameters that are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Parameters that are derived mainly from simulations. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 238: Power Supply

    Current Injection Power supply must maintain regulation within operating V or V range during instantaneous and operating maximum current conditions. If positive injection current (V > V ) is greater than I , the MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 239: Absolute Maximum Ratings

    AC over or undershoots for ±2V beyond the supply if limited to 20ns length are allowed. All digital I/O pins are internally clamped to V and V and V or V and V Those pins are internally clamped to V and V SSOSC DDOSC MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 240: Esd Protection And Latch-Up Immunity

    T Human Body Model (HBM) 2000 T Machine Model (MM) T Charge Device Model (CDM) T Latch-up Current at T = 125°C positive +100 negative -100 T Latch-up Current at T = 27°C positive +200 negative -200 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 241: Operating Conditions

    The average chip-junction temperature (T obtained from: ⋅ Θ Eqn. A-1 = Junction Temperature [°C] = Ambient Temperature [°C] = Total Chip Power Dissipation [W] Θ = Package Thermal Resistance [°C/W] MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 242 VDDR, which additionally contains the current flowing into the external loads with output high. ∑ ⋅ Eqn. A-8 DSON is the sum of all output currents on I/O ports associated with VDDX and VDDR. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 243: Table A-5. Thermal Package Simulation Details

    Reported value includes the thermal resistance of the interface layer. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 244: I/O Characteristics

    Input Capacitance (input, input/output pins) Injection Current Single Pin Limit -2.5 Total Device Limit. Sum of all injected currents Load Capacitance 50% Partial Drive 100% Full Drive Refer to Section A.1.4, “Current Injection”, for more information. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 245: Table A-7. 3.3V I/O Characteristics (Vdd5 = 3.3V)

    Input Capacitance (input, input/output pins) Injection Current Single Pin Limit -2.5 Total Device Limit. Sum of all injected currents Load Capacitance 50% Partial Drive 100% Full Drive Refer to Section A.1.4, “Current Injection” for more information. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 246: Supply Currents

    EXTAL input. Table A-8. Supply Current Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Unit P Run supply currents -40°C Internal regulator enabled 25°C 140°C MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 247: Voltage Regulator (Vreg)

    — — LVRA Power-on Reset Assert Level 0.97 — — PORA Deassert Level — — 2.07 PORD High Impedance Output High Impedance Output Monitors V , always active Monitors V , always active MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 248: Chip Power-Up And Voltage Drops

    The capacitive loads are specified in Figure A-10. Ceramic capacitors with X7R dielectricum are required. Table A-10. Voltage Regulator Recommended Capacitive Loads Characteristic Symbol Typical Unit VDD external capacitive load 12000 DDext VDDOSC external capacitive load 5000 DDOSCext MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 249: Reset And Oscillator

    External Reset When external reset is asserted for a time greater than PW the CRG module generates an internal RSTL reset, and the CC starts operations, if there was an oscillation before reset. MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 250: Oscillator

    The input/output pins D[15:0] are in a high-impedance state when the device is not selected (CE# is HIGH), the outputs are disabled (OE# HIGH) or during a write operation (CE# LOW, and WE# LOW). MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 251: Figure A-2. Ami Interface Read Timing Diagram

    ADDRESS BSEL[1:0]# BYTE SELECT D[15:0] DATA OEWE WEOE Note: The signal FUNC2 is a logical OR of the chip enable (CE#) and write enable (WE#) inputs. Figure A-3. AMI Interface Write Timing Diagram MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 252: Mpc Interface Timing

    The input/output pins (D[15:0]) are in a high-impedance state when the device is not selected (CE# is HIGH), the outputs are disabled (OE# HIGH) or during a write operation (CE# LOW and at least one BSEL[1:0]# LOW). MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 253: Figure A-4. Mpc Interface Read Timing Diagram

    ADDRESS D[15:0] DATA OEBSEL BSELOE Note: The signal FUNC4 is a logical OR of the chip enable (CE#) and the logically ANDed byte select (BSEL[1:0]#) inputs. Figure A-5. MPC Interface Write Timing Diagram MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 254: Table A-14. Mpc Interface Ac Switching Characteristics Over The Operating Range

    Depends on duty cycle of the CHI and host interface clock: t ) - t + 27, CHICLK_CC CHICLK_CC_HIGH where t is the period in ns of the high phase of the CHI and host interface clock. CHICLK_CC_HIGH MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 255: Hcs12 Interface Timing

    PA[0:7], PB[0:7] ADDRESS DATA XADDR[19:14] ADDRESS RW_CC# ACS[2:0] Figure A-6. HCS12 Interface Read Timing Diagram ECLK_CC PA[0:7], PB[0:7] ADDRESS DATA XADDR[19:14] ADDRESS RW_CC# ACS[2:0] LSTRB LOW STROBE Figure A-7. HCS12 Interface Write Timing Diagram MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 256: Table A-15. Hcs12 Interface Ac Switching Characteristics Over The Operating Range

    Depends on duty cycle of EXTAL/CLK_CC: t = 99 + (t , where t is the period in CLK_CC CLK_CC_HIGH CLK_CC ns of EXTAL/CLK_CC and t is the period in ns of the high phase of EXTAL/CLK_CC. CLK_CC_HIGH MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 257: Figure B-1. 64-Pin Lqfp Mechanical Dimensions (Case N 840F-02)

    Package Information Appendix B Package Information 64-pin LQFP package Figure B-1. 64-pin LQFP Mechanical Dimensions (Case N 840F-02) (Page 1) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 258: Figure B-2. 64-Pin Lqfp Mechanical Dimensions (Case N 840F-02)

    Package Information Figure B-2. 64-pin LQFP Mechanical Dimensions (Case N 840F-02) (Page 2) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 259: Figure B-3. 64-Pin Lqfp Mechanical Dimensions (Case N 840F-02)

    Package Information Figure B-3. 64-pin LQFP Mechanical Dimensions (Case N 840F-02) (Page 3) MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 260 Package Information MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 261: Table C-1. Suggested External Component Values

    100– 220nF VDDR, VDDX filter cap ceramic X7R/tantalum 100– 220nF Cload VDD2_5 filter cap ceramic X7R 100– 220nF OSC resistance 1 MΩ 0 Ω (i.e. short-circuit) OSC resistance Quartz NDK NX8045GA 40 MHz MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 262: Figure C-1. Recommended Pcb Layout (64-Pin Lqfp) For Standard Pierce Oscillator Mode

    C1 = C2 = 2pF Rb = 1MΩ Rs = 0Ω (i.e. short circuit) VSSOSC C3 = Cload = 220nF Cd = 100nF Figure C-1. Recommended PCB Layout (64-pin LQFP) for Standard Pierce Oscillator Mode MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 263 Message Buffer Cycle Counter Filter Registers (MBCCFRn) 132 Message Buffer Data Size Register (MBDSR) 75 Message Buffer Frame ID Registers (MBFIDRn) 133 Message Buffer Index Registers (MBIDXRn) 133 Message Buffer Interrupt Vector Register (MBIVEC) 88 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...

  • Page 264: Figure 3-35. Network Management Vector Length Register (Nmvlr)

    Protocol Configuration Register 25 (PCR25) 128 Protocol Configuration Register 26 (PCR26) 128 Protocol Configuration Register 27 (PCR27) 129 Protocol Configuration Register 28 (PCR28) 129 Protocol Configuration Register 29 (PCR29) 129 Protocol Configuration Register 3 (PCR3) 124 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 265 Slot Status Selection Register (SSSR) 108 Strobe Signal Control Register (STBSCR) 72 Sync Frame Counter Register (SFCNTR) 100 Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR) 103 Sync Frame ID Acceptance Filter Value Register (SFIDAFVR) 103 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 266 Timer 1 Cycle Set Register (TI1CYSR) 106 Timer 1 Macrotick Offset Register (TI1MTOR) 106 Timer 2 Configuration Register 0 (TI2CR0) 107 Timer 2 Configuration Register 1 (TI2CR1) 107 Timer Configuration and Control Register (TICCR) 105 MFR4310 Reference Manual, Rev. 2 Freescale Semiconductor...
  • Page 268 Freescale Semiconductor makes no warranty, representation or www.freescale.com/support guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH...

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