Transmission Formats; Data Transmission Length; Data Shift Ordering; Clock Phase And Polarity Controls - Freescale Semiconductor 56F800 User Manual

11.5 Transmission Formats

During a SPI transmission, data is simultaneously transmitted (shifted out serially) and received
(shifted in serially). A serial clock synchronizes shifting and sampling on the two serial data
lines. A slave select line allows selection of an individual slave SPI device; slave devices not
selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can
optionally be used to indicate multiple-master bus contention.

11.5.1 Data Transmission Length

The SPI can support data lengths from two to 16 bits. This can be configured in the Data Size
Register (SPDSR). When the data length is less than 16 bits, the Receive Data register will pad
the upper bits with zeros.
Note: Data can be lost if the data length is not the same for both master and slave devices.

11.5.2 Data Shift Ordering

The SPI can be configured to transmit or receive the MSB of the desired data first or last. This is
controlled by the Data Shift Order (DSO) bit in the SPSCR. Regardless which bit is transmitted
or received first, the data shall always be written to the SPDTR and read from the Receive Data
Register (SPDRR) with the LSB in bit zero and the MSB in the correct position, depending on the
data transmission size.

11.5.3 Clock Phase and Polarity Controls

Software can select any of four combinations of Serial Clock (SCLK) phase and polarity using
two bits in the SPSCR. The Clock Polarity is specified by the (CPOL) control bit. In turn, it
selects an active high or low clock and has no significant effect on the transmission format.
The Clock Phase (CPHA) control bit selects one of two fundamentally different transmission
formats. The clock phase and polarity should be identical for the master SPI device and the
communicating slave device. In some cases, the phase and polarity are changed between
transmissions to allow a master device to communicate with peripheral slaves having different
requirements.
Note: Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing the SPI
Enable (SPE) bit.
Freescale Semiconductor
Serial Peripheral Interface (SPI), Rev. 3
Transmission Formats
9