Freescale Semiconductor 56F800 User Manual page 337

SSI is capable of finding the start of the next frame automatically when the word is completely
received, it is transferred to the SRX register, setting the Receive Data Ready bit. Setting the
RDR bit causes a receive interrupt to occur if the receiver interrupt is enabled, or the Receiver
Interrupt Enable (RIE) bit is set. The second data word, second time slot in the frame, begins
shifting in immediately after the transfer of the first data word to the SRX register. The program
has to read the data from the receive data register, clearing Receive Data Full (RDF) before the
second data word is completely received and is ready to transfer to RX data register, or a receiver
overrun error occurs, causing the ROE bit to set.
An interrupt can occur after the reception of each enabled data word, or the programmer can poll
the RDF flag. The SSI program response can be one of the following:
• Read RX and use the data
• Read RX and ignore the data
• Do nothing—the receiver overrun exception occurs at the end of the current time slot
Note: For a continuous clock, the optional frame synchronization output and clock output
signals are not affected, even if the transmitter or receiver is disabled. TE and RE do
not disable the bit clock or the frame synchronization generation. The only way to
disable the bit clock and the frame synchronization generation is to disable the SSIEN
bit in the SCR2.
The transmitter and receiver timing for an 8-bit word with a continuous clock, FIFO disabled,
and three words per frame synchronization in the network mode is shown in
Figure 12-26.
Freescale Semiconductor
Synchronous Serial Interface (SSI), Rev. 3
Operating Modes
41