Jtag/Once Port; Quad Timer Module (Tmr) - Freescale Semiconductor 56F800 User Manual

Peripheral Descriptions
1. A Watchdog Timer
2. An interrupt generator
These two functions monitor processor activity and provide an automatic reset signal if a failure
occurs. Both functions are contained in the same block because the input clock for both comes
from a common clock divider:
• 12-bit counter to provide 4096 different timeout periods
• COP timebase is the CPU clock divided by 16384
• At 80MHz, minimum timeout period is 204.8
µ
204.8 s

1.10.6 JTAG/OnCE Port

The JTAG/OnCE port introduces the 56F826/827 into a target system while retaining debug
control. The JTAG port provides board-level testing capability for scan-based emulation
compatible with the IEEE 1149.1a-1993 IEEE Standard Test Access Port and Boundary Scan
Architecture specification defined by the JTAG. Five dedicated pins interface to a Test Access
Port (TAP) containing a 16-state controller.
The OnCE module interacts in a debug environment with the 56800 core and its peripherals
nonintrusively. Its capabilities include:
• Examining registers, memory, or on-chip peripherals
• Setting breakpoints in memory
• Stepping or tracing instructions
The OnCE module provides simple, inexpensive, and speed-independent access to the DSP56800
core for sophisticated debugging and economical system development. The JTAG/OnCE port
provides access to the OnCE module. Through the 56F80x to its target system, it retains debug
control without sacrificing other accessible on-chip resources.

1.10.7 Quad Timer Module (TMR)

• 56F826
— Timer A with four pins
• 56F827
— Timer A with four pins
Quad timer features:
• Four channels, independently programmable as input capture or output compare
24
µ
s, maximum is 839ms, with a resolution of
56F826/827 User Manual, Rev. 3
Freescale Semiconductor